PIPELINE ARCHITECTURE OF H.264/AVC STANDARD CABAC DECODER FOR MOBILE APPLICATIONS
The paper describes a three-stage pipeline architecture implementation of the CABAC decoder for mobile applications, with image resolution up to 625SD. The decoder architecture is suggested for pipeline calculations with the decoding performance of one bin per clock cycle. The decoder is compatible...
| Main Authors: | , , |
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| Format: | Article |
| Language: | Russian |
| Published: |
The United Institute of Informatics Problems of the National Academy of Sciences of Belarus
2016-10-01
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| Series: | Informatika |
| Online Access: | https://inf.grid.by/jour/article/view/95 |
| Summary: | The paper describes a three-stage pipeline architecture implementation of the CABAC decoder for mobile applications, with image resolution up to 625SD. The decoder architecture is suggested for pipeline calculations with the decoding performance of one bin per clock cycle. The decoder is compatible with profiles high profile, high 10 profile and high 4:2:2 profile and supports regime MBAFF and 8×8 blocks. It is scalable both in the resolution and in the supported decoding tools described in standard H.264. A comparison of our implementation with implementations of a prototype CABAC decoder on FPGA from the company Xilinx is given. |
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| ISSN: | 1816-0301 |