PIPELINE ARCHITECTURE OF H.264/AVC STANDARD CABAC DECODER FOR MOBILE APPLICATIONS

The paper describes a three-stage pipeline architecture implementation of the CABAC decoder for mobile applications, with image resolution up to 625SD. The decoder architecture is suggested for pipeline calculations with the decoding performance of one bin per clock cycle. The decoder is compatible...

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Main Authors: Al. A. Petrovsky, A. V. Stankevich, A. A. Petrovsky
Format: Article
Language:Russian
Published: The United Institute of Informatics Problems of the National Academy of Sciences of Belarus 2016-10-01
Series:Informatika
Online Access:https://inf.grid.by/jour/article/view/95
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author Al. A. Petrovsky
A. V. Stankevich
A. A. Petrovsky
author_facet Al. A. Petrovsky
A. V. Stankevich
A. A. Petrovsky
author_sort Al. A. Petrovsky
collection DOAJ
description The paper describes a three-stage pipeline architecture implementation of the CABAC decoder for mobile applications, with image resolution up to 625SD. The decoder architecture is suggested for pipeline calculations with the decoding performance of one bin per clock cycle. The decoder is compatible with profiles high profile, high 10 profile and high 4:2:2 profile and supports regime MBAFF and 8×8 blocks. It is scalable both in the resolution and in the supported decoding tools described in standard H.264. A comparison of our implementation with implementations of a prototype CABAC decoder on FPGA from the company Xilinx is given.
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spelling doaj.art-9ea81a3f8a774f94bb8721cdc258253a2023-03-13T08:32:17ZrusThe United Institute of Informatics Problems of the National Academy of Sciences of BelarusInformatika1816-03012016-10-0103213394PIPELINE ARCHITECTURE OF H.264/AVC STANDARD CABAC DECODER FOR MOBILE APPLICATIONSAl. A. Petrovsky0A. V. Stankevich1A. A. Petrovsky2Белорусский государственный университет информатики и радиоэлектроникиБелорусский государственный университет информатики и радиоэлектроникиБелорусский государственный университет информатики и радиоэлектроникиThe paper describes a three-stage pipeline architecture implementation of the CABAC decoder for mobile applications, with image resolution up to 625SD. The decoder architecture is suggested for pipeline calculations with the decoding performance of one bin per clock cycle. The decoder is compatible with profiles high profile, high 10 profile and high 4:2:2 profile and supports regime MBAFF and 8×8 blocks. It is scalable both in the resolution and in the supported decoding tools described in standard H.264. A comparison of our implementation with implementations of a prototype CABAC decoder on FPGA from the company Xilinx is given.https://inf.grid.by/jour/article/view/95
spellingShingle Al. A. Petrovsky
A. V. Stankevich
A. A. Petrovsky
PIPELINE ARCHITECTURE OF H.264/AVC STANDARD CABAC DECODER FOR MOBILE APPLICATIONS
Informatika
title PIPELINE ARCHITECTURE OF H.264/AVC STANDARD CABAC DECODER FOR MOBILE APPLICATIONS
title_full PIPELINE ARCHITECTURE OF H.264/AVC STANDARD CABAC DECODER FOR MOBILE APPLICATIONS
title_fullStr PIPELINE ARCHITECTURE OF H.264/AVC STANDARD CABAC DECODER FOR MOBILE APPLICATIONS
title_full_unstemmed PIPELINE ARCHITECTURE OF H.264/AVC STANDARD CABAC DECODER FOR MOBILE APPLICATIONS
title_short PIPELINE ARCHITECTURE OF H.264/AVC STANDARD CABAC DECODER FOR MOBILE APPLICATIONS
title_sort pipeline architecture of h 264 avc standard cabac decoder for mobile applications
url https://inf.grid.by/jour/article/view/95
work_keys_str_mv AT alapetrovsky pipelinearchitectureofh264avcstandardcabacdecoderformobileapplications
AT avstankevich pipelinearchitectureofh264avcstandardcabacdecoderformobileapplications
AT aapetrovsky pipelinearchitectureofh264avcstandardcabacdecoderformobileapplications