Locking-Enabled Security Analysis of Cryptographic Circuits
Hardware implementations of cryptographic primitives require protection against physical attacks and supply chain threats. This raises the question of <i>secure composability</i> of different attack countermeasures, i.e., whether protecting a circuit against one threat can make it more v...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2024-01-01
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| Series: | Cryptography |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2410-387X/8/1/2 |
| _version_ | 1827306636998344704 |
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| author | Devanshi Upadhyaya Maël Gay Ilia Polian |
| author_facet | Devanshi Upadhyaya Maël Gay Ilia Polian |
| author_sort | Devanshi Upadhyaya |
| collection | DOAJ |
| description | Hardware implementations of cryptographic primitives require protection against physical attacks and supply chain threats. This raises the question of <i>secure composability</i> of different attack countermeasures, i.e., whether protecting a circuit against one threat can make it more vulnerable against a different threat. In this article, we study the consequences of applying logic locking, a popular design-for-trust solution against intellectual property piracy and overproduction, to cryptographic circuits. We show that the ability to unlock the circuit incorrectly gives the adversary new powerful attack options. We introduce LEDFA (locking-enabled differential fault analysis) and demonstrate for several ciphers and families of locking schemes that fault attacks become possible (or consistently easier) for incorrectly unlocked circuits. In several cases, logic locking has made circuit implementations prone to classical algebraic attacks with no fault injection needed altogether. We refer to this “zero-fault” version of LEDFA by the term LEDA, investigate its success factors in-depth and propose a countermeasure to protect the logic-locked implementations against LEDA. We also perform test vector leakage assessment (TVLA) of incorrectly unlocked AES implementations to show the effects of logic locking regarding side-channel leakage. Our results indicate that logic locking is not safe to use in cryptographic circuits, making them less rather than more secure. |
| first_indexed | 2024-04-24T18:24:47Z |
| format | Article |
| id | doaj.art-9ebed823f2bf4f289538d906ef858121 |
| institution | Directory Open Access Journal |
| issn | 2410-387X |
| language | English |
| last_indexed | 2024-04-24T18:24:47Z |
| publishDate | 2024-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Cryptography |
| spelling | doaj.art-9ebed823f2bf4f289538d906ef8581212024-03-27T13:32:18ZengMDPI AGCryptography2410-387X2024-01-0181210.3390/cryptography8010002Locking-Enabled Security Analysis of Cryptographic CircuitsDevanshi Upadhyaya0Maël Gay1Ilia Polian2Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, GermanyInstitut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, GermanyInstitut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, GermanyHardware implementations of cryptographic primitives require protection against physical attacks and supply chain threats. This raises the question of <i>secure composability</i> of different attack countermeasures, i.e., whether protecting a circuit against one threat can make it more vulnerable against a different threat. In this article, we study the consequences of applying logic locking, a popular design-for-trust solution against intellectual property piracy and overproduction, to cryptographic circuits. We show that the ability to unlock the circuit incorrectly gives the adversary new powerful attack options. We introduce LEDFA (locking-enabled differential fault analysis) and demonstrate for several ciphers and families of locking schemes that fault attacks become possible (or consistently easier) for incorrectly unlocked circuits. In several cases, logic locking has made circuit implementations prone to classical algebraic attacks with no fault injection needed altogether. We refer to this “zero-fault” version of LEDFA by the term LEDA, investigate its success factors in-depth and propose a countermeasure to protect the logic-locked implementations against LEDA. We also perform test vector leakage assessment (TVLA) of incorrectly unlocked AES implementations to show the effects of logic locking regarding side-channel leakage. Our results indicate that logic locking is not safe to use in cryptographic circuits, making them less rather than more secure.https://www.mdpi.com/2410-387X/8/1/2cryptographylogic lockingfault attacksside channel analysis |
| spellingShingle | Devanshi Upadhyaya Maël Gay Ilia Polian Locking-Enabled Security Analysis of Cryptographic Circuits Cryptography cryptography logic locking fault attacks side channel analysis |
| title | Locking-Enabled Security Analysis of Cryptographic Circuits |
| title_full | Locking-Enabled Security Analysis of Cryptographic Circuits |
| title_fullStr | Locking-Enabled Security Analysis of Cryptographic Circuits |
| title_full_unstemmed | Locking-Enabled Security Analysis of Cryptographic Circuits |
| title_short | Locking-Enabled Security Analysis of Cryptographic Circuits |
| title_sort | locking enabled security analysis of cryptographic circuits |
| topic | cryptography logic locking fault attacks side channel analysis |
| url | https://www.mdpi.com/2410-387X/8/1/2 |
| work_keys_str_mv | AT devanshiupadhyaya lockingenabledsecurityanalysisofcryptographiccircuits AT maelgay lockingenabledsecurityanalysisofcryptographiccircuits AT iliapolian lockingenabledsecurityanalysisofcryptographiccircuits |