A High-Performance FPGA-Based Depthwise Separable Convolution Accelerator

A High-Performance FPGA-Based Depthwise Separable Convolution Accelerator

Depthwise separable convolution (DSC) significantly reduces parameter and floating operations with an acceptable loss of accuracy and has been widely used in various lightweight convolutional neural network (CNN) models. In practical applications, however, DSC accelerators based on graphics processi...

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Bibliographic Details
Main Authors:	Jiye Huang, Xin Liu, Tongdong Guo, Zhijin Zhao
Format:	Article
Language:	English
Published:	MDPI AG 2023-03-01
Series:	Electronics
Subjects:	convolutional neural network depthwise separable convolution field programmable gate array hardware accelerator MobileNetV2
Online Access:	https://www.mdpi.com/2079-9292/12/7/1571

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