IMPLEMENTATION OF FPGA-BASED RISC FOR LNS ARITHMETIC BY SOFTWARE & HARDWARE
ield Programmable Gate Arrays (FPGAs) have some difficulty with the implementation of deating-point operations. In particular, devoting the large number of slices needed by floating-point multipliers prohibits incorporating floating point into smaller, less expensive FPGAs. An alternative is the Lo...
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| Format: | Article |
| Language: | English |
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University of Baghdad
2006-03-01
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| Series: | Journal of Engineering |
| Online Access: | https://www.joe.uobaghdad.edu.iq/index.php/main/article/view/2958 |