Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing
Convolution operations have a significant influence on the overall performance of a convolutional neural network, especially in edge-computing hardware design. In this paper, we propose a low-power signed convolver hardware architecture that is well suited for low-power edge computing. The basic ide...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-07-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/21/15/5081 |
| _version_ | 1797525131980963840 |
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| author | Hsu-Yu Kao Xin-Jia Chen Shih-Hsu Huang |
| author_facet | Hsu-Yu Kao Xin-Jia Chen Shih-Hsu Huang |
| author_sort | Hsu-Yu Kao |
| collection | DOAJ |
| description | Convolution operations have a significant influence on the overall performance of a convolutional neural network, especially in edge-computing hardware design. In this paper, we propose a low-power signed convolver hardware architecture that is well suited for low-power edge computing. The basic idea of the proposed convolver design is to combine all multipliers’ final additions and their corresponding adder tree to form a partial product matrix (PPM) and then to use the reduction tree algorithm to reduce this PPM. As a result, compared with the state-of-the-art approach, our convolver design not only saves a lot of carry propagation adders but also saves one clock cycle per convolution operation. Moreover, the proposed convolver design can be adapted for different dataflows (including input stationary dataflow, weight stationary dataflow, and output stationary dataflow). According to dataflows, two types of convolve-accumulate units are proposed to perform the accumulation of convolution results. The results show that, compared with the state-of-the-art approach, the proposed convolver design can save 15.6% power consumption. Furthermore, compared with the state-of-the-art approach, on average, the proposed convolve-accumulate units can reduce 15.7% power consumption. |
| first_indexed | 2024-03-10T09:09:22Z |
| format | Article |
| id | doaj.art-a013f5617e594c0982dd87651960d11e |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-10T09:09:22Z |
| publishDate | 2021-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-a013f5617e594c0982dd87651960d11e2023-11-22T06:10:13ZengMDPI AGSensors1424-82202021-07-012115508110.3390/s21155081Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge ComputingHsu-Yu Kao0Xin-Jia Chen1Shih-Hsu Huang2Department of Electronic Engineering, Chung Yuan Christian University, Taoyuan 32023, TaiwanDepartment of Electronic Engineering, Chung Yuan Christian University, Taoyuan 32023, TaiwanDepartment of Electronic Engineering, Chung Yuan Christian University, Taoyuan 32023, TaiwanConvolution operations have a significant influence on the overall performance of a convolutional neural network, especially in edge-computing hardware design. In this paper, we propose a low-power signed convolver hardware architecture that is well suited for low-power edge computing. The basic idea of the proposed convolver design is to combine all multipliers’ final additions and their corresponding adder tree to form a partial product matrix (PPM) and then to use the reduction tree algorithm to reduce this PPM. As a result, compared with the state-of-the-art approach, our convolver design not only saves a lot of carry propagation adders but also saves one clock cycle per convolution operation. Moreover, the proposed convolver design can be adapted for different dataflows (including input stationary dataflow, weight stationary dataflow, and output stationary dataflow). According to dataflows, two types of convolve-accumulate units are proposed to perform the accumulation of convolution results. The results show that, compared with the state-of-the-art approach, the proposed convolver design can save 15.6% power consumption. Furthermore, compared with the state-of-the-art approach, on average, the proposed convolve-accumulate units can reduce 15.7% power consumption.https://www.mdpi.com/1424-8220/21/15/5081adder treesconvolution operationsdataflowdigital circuitslogic designmultiplications |
| spellingShingle | Hsu-Yu Kao Xin-Jia Chen Shih-Hsu Huang Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing Sensors adder trees convolution operations dataflow digital circuits logic design multiplications |
| title | Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing |
| title_full | Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing |
| title_fullStr | Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing |
| title_full_unstemmed | Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing |
| title_short | Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing |
| title_sort | convolver design and convolve accumulate unit design for low power edge computing |
| topic | adder trees convolution operations dataflow digital circuits logic design multiplications |
| url | https://www.mdpi.com/1424-8220/21/15/5081 |
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