Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems
A two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching....
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-01-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/3/328 |
| _version_ | 1797488396492341248 |
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| author | Mayar Ali Hesham F. A. Hamed Ghazal A. Fahmy |
| author_facet | Mayar Ali Hesham F. A. Hamed Ghazal A. Fahmy |
| author_sort | Mayar Ali |
| collection | DOAJ |
| description | A two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching. The shunt peaking topology in a common source configuration is adopted at the second stage to enhance the power gain. The postlayout simulation is performed using the TSMC 65 nm CMOS process operating in a frequency band of 3.1 GHz to 10.6 GHz. The postlayout simulation results indicate that a high flat gain of approximately 22.8 ± 1.2 dB, small group delay variation of ±50 ps, and good input and output matching of less than −10 dB are achieved over the desired working band. Moreover, a saturated output power of 10 dBm and maximum power-added efficiency (PAE) of 29.5% is achieved at 6 GHz. The proposed PA consumes the low power of 15.5 mW from 1.2 V supply voltage. |
| first_indexed | 2024-03-10T00:01:33Z |
| format | Article |
| id | doaj.art-a029866d82814ba19c8e667db36452d4 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T00:01:33Z |
| publishDate | 2022-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-a029866d82814ba19c8e667db36452d42023-11-23T16:15:07ZengMDPI AGElectronics2079-92922022-01-0111332810.3390/electronics11030328Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB SystemsMayar Ali0Hesham F. A. Hamed1Ghazal A. Fahmy2Higher Institute of Engineering and Technology, New Minia 11765, EgyptFaculty of Engineering, Minia University, Minia 61519, EgyptNational Telecommunications Institute (NTI), Cairo 11768, EgyptA two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching. The shunt peaking topology in a common source configuration is adopted at the second stage to enhance the power gain. The postlayout simulation is performed using the TSMC 65 nm CMOS process operating in a frequency band of 3.1 GHz to 10.6 GHz. The postlayout simulation results indicate that a high flat gain of approximately 22.8 ± 1.2 dB, small group delay variation of ±50 ps, and good input and output matching of less than −10 dB are achieved over the desired working band. Moreover, a saturated output power of 10 dBm and maximum power-added efficiency (PAE) of 29.5% is achieved at 6 GHz. The proposed PA consumes the low power of 15.5 mW from 1.2 V supply voltage.https://www.mdpi.com/2079-9292/11/3/328power amplifierultra-wide bandlow-power applicationswireless communication |
| spellingShingle | Mayar Ali Hesham F. A. Hamed Ghazal A. Fahmy Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems Electronics power amplifier ultra-wide band low-power applications wireless communication |
| title | Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems |
| title_full | Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems |
| title_fullStr | Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems |
| title_full_unstemmed | Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems |
| title_short | Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems |
| title_sort | small group delay variation and high efficiency 3 1 10 6 ghz cmos power amplifier for uwb systems |
| topic | power amplifier ultra-wide band low-power applications wireless communication |
| url | https://www.mdpi.com/2079-9292/11/3/328 |
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