Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology
The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-o...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-12-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/22/1/121 |
| _version_ | 1797497653206974464 |
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| author | Mattia Cicalini Massimo Piotto Paolo Bruschi Michele Dei |
| author_facet | Mattia Cicalini Massimo Piotto Paolo Bruschi Michele Dei |
| author_sort | Mattia Cicalini |
| collection | DOAJ |
| description | The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. Here, we analyse and design a capacitance-to-digital converter, based on the recently introduced iterative delay-chain discharge architecture, showing the circuit inner operating principles and the correspondent design trade-offs. A complete design case, implemented in a commercial 180 nm CMOS process, operating at 0.9 V supply for a 0–250 pF input capacitance range, is presented. The circuit, tested by means of detailed electrical simulations, shows ultra-low energy consumption (≤1.884 nJ/conversion), excellent linearity (linearity error 15.26 ppm), good robustness against process and temperature corners (conversion gain sensitivity to process corners variation of 114.0 ppm and maximum temperature sensitivity of 81.9 ppm/<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mo>°</mo></semantics></math></inline-formula>C in the −40 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mo>°</mo></semantics></math></inline-formula>C, +125 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mo>°</mo></semantics></math></inline-formula>C interval) and medium-low resolution of 10.3 effective number of bits, while using only 0.0192 mm<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mrow></mrow><mn>2</mn></msup></semantics></math></inline-formula> of silicon area and employing 2.93 ms for a single conversion. |
| first_indexed | 2024-03-10T03:22:18Z |
| format | Article |
| id | doaj.art-a08e5164a7cb4613b510fb413503dbc1 |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-10T03:22:18Z |
| publishDate | 2021-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-a08e5164a7cb4613b510fb413503dbc12023-11-23T12:17:13ZengMDPI AGSensors1424-82202021-12-0122112110.3390/s22010121Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS TechnologyMattia Cicalini0Massimo Piotto1Paolo Bruschi2Michele Dei3Department of Information Engineering, University of Pisa, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, 56122 Pisa, ItalyThe design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. Here, we analyse and design a capacitance-to-digital converter, based on the recently introduced iterative delay-chain discharge architecture, showing the circuit inner operating principles and the correspondent design trade-offs. A complete design case, implemented in a commercial 180 nm CMOS process, operating at 0.9 V supply for a 0–250 pF input capacitance range, is presented. The circuit, tested by means of detailed electrical simulations, shows ultra-low energy consumption (≤1.884 nJ/conversion), excellent linearity (linearity error 15.26 ppm), good robustness against process and temperature corners (conversion gain sensitivity to process corners variation of 114.0 ppm and maximum temperature sensitivity of 81.9 ppm/<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mo>°</mo></semantics></math></inline-formula>C in the −40 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mo>°</mo></semantics></math></inline-formula>C, +125 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mo>°</mo></semantics></math></inline-formula>C interval) and medium-low resolution of 10.3 effective number of bits, while using only 0.0192 mm<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mrow></mrow><mn>2</mn></msup></semantics></math></inline-formula> of silicon area and employing 2.93 ms for a single conversion.https://www.mdpi.com/1424-8220/22/1/121capacitance-to-digital converteriterative-delay-chain dischargeCMOS capacitive sensor interface |
| spellingShingle | Mattia Cicalini Massimo Piotto Paolo Bruschi Michele Dei Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology Sensors capacitance-to-digital converter iterative-delay-chain discharge CMOS capacitive sensor interface |
| title | Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology |
| title_full | Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology |
| title_fullStr | Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology |
| title_full_unstemmed | Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology |
| title_short | Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology |
| title_sort | design of a capacitance to digital converter based on iterative delay chain discharge in 180 nm cmos technology |
| topic | capacitance-to-digital converter iterative-delay-chain discharge CMOS capacitive sensor interface |
| url | https://www.mdpi.com/1424-8220/22/1/121 |
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