A Novel Memory-centric Architecture and Organization of Processors and Computers
The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, propose...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Anhalt University of Applied Sciences
2015-03-01
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| Series: | Proceedings of the International Conference on Applied Innovations in IT |
| Subjects: | |
| Online Access: | https://icaiit.org/paper.php?paper=3rd_ICAIIT/9 |
| _version_ | 1797803478684270592 |
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| author | Danijela Efnusheva Goce Dokoski Aristotel Tentov Marija Kalendar |
| author_facet | Danijela Efnusheva Goce Dokoski Aristotel Tentov Marija Kalendar |
| author_sort | Danijela Efnusheva |
| collection | DOAJ |
| description | The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network. |
| first_indexed | 2024-03-13T05:22:27Z |
| format | Article |
| id | doaj.art-a0ec62c2352d4cc4aee631353dc0d9ef |
| institution | Directory Open Access Journal |
| issn | 2199-8876 |
| language | English |
| last_indexed | 2024-03-13T05:22:27Z |
| publishDate | 2015-03-01 |
| publisher | Anhalt University of Applied Sciences |
| record_format | Article |
| series | Proceedings of the International Conference on Applied Innovations in IT |
| spelling | doaj.art-a0ec62c2352d4cc4aee631353dc0d9ef2023-06-15T11:59:02ZengAnhalt University of Applied SciencesProceedings of the International Conference on Applied Innovations in IT2199-88762015-03-0131475310.13142/kt10003.09A Novel Memory-centric Architecture and Organization of Processors and ComputersDanijela Efnusheva0https://orcid.org/0000-0002-6069-1865Goce Dokoski1Aristotel Tentov2Marija Kalendar3https://orcid.org/0000-0002-4226-0690SS. Cyril and Methodius University - Faculty of Electrical Engineering and Information Technologies Karpos II bb, PO Box 574, 1000 Skopje, MacedoniaSS. Cyril and Methodius University - Faculty of Electrical Engineering and Information Technologies Karpos II bb, PO Box 574, 1000 Skopje, MacedoniaSS. Cyril and Methodius University - Faculty of Electrical Engineering and Information Technologies Karpos II bb, PO Box 574, 1000 Skopje, MacedoniaSS. Cyril and Methodius University - Faculty of Electrical Engineering and Information Technologies Karpos II bb, PO Box 574, 1000 Skopje, MacedoniaThe modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.https://icaiit.org/paper.php?paper=3rd_ICAIIT/9explicit parallelismfield programmable gate array (fpga)high-performance computingprocessor architecture and organizationprocessing in memory |
| spellingShingle | Danijela Efnusheva Goce Dokoski Aristotel Tentov Marija Kalendar A Novel Memory-centric Architecture and Organization of Processors and Computers Proceedings of the International Conference on Applied Innovations in IT explicit parallelism field programmable gate array (fpga) high-performance computing processor architecture and organization processing in memory |
| title | A Novel Memory-centric Architecture and Organization of Processors and Computers |
| title_full | A Novel Memory-centric Architecture and Organization of Processors and Computers |
| title_fullStr | A Novel Memory-centric Architecture and Organization of Processors and Computers |
| title_full_unstemmed | A Novel Memory-centric Architecture and Organization of Processors and Computers |
| title_short | A Novel Memory-centric Architecture and Organization of Processors and Computers |
| title_sort | novel memory centric architecture and organization of processors and computers |
| topic | explicit parallelism field programmable gate array (fpga) high-performance computing processor architecture and organization processing in memory |
| url | https://icaiit.org/paper.php?paper=3rd_ICAIIT/9 |
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