Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning
Over the past few years, the computation capability of field-programmable gate arrays (FPGAs) has increased tremendously. This has led to the increase in the complexity of the designs implemented on FPGAs and to the time taken by the FPGA back-end flow. The FPGA back-end flow comprises of many steps...
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| Format: | Article |
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MDPI AG
2022-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/14/2240 |
| _version_ | 1797433683209093120 |
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| author | Imran Baig Umer Farooq |
| author_facet | Imran Baig Umer Farooq |
| author_sort | Imran Baig |
| collection | DOAJ |
| description | Over the past few years, the computation capability of field-programmable gate arrays (FPGAs) has increased tremendously. This has led to the increase in the complexity of the designs implemented on FPGAs and to the time taken by the FPGA back-end flow. The FPGA back-end flow comprises of many steps, and routing is one of the most critical steps among them. Routing normally constitutes more than 50% of the total time taken by the back-end flow and an optimization at this step can lead to overall optimization of the back-end flow. In this work, we propose enhancements to the routing step by incorporating a reinforcement learning (RL)-based framework. In the proposed RL-based framework, we use the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>ϵ</mi></semantics></math></inline-formula>-greedy approach and customized reward functions to speed up the routing step while maintaining similar or better quality of results (QoR) as compared to the conventional negotiation-based congestion-driven routing solution. For experimentation, we use two sets of widely deployed, large heterogeneous benchmarks. Our results show that, for the RL-based framework, the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>ϵ</mi></semantics></math></inline-formula>-greedy greedy approach combined with a modified reward function gives better results as compared to purely greedy or exploratory approaches. Moreover, the incorporation of the proposed reward function in the RL-based framework and its comparison with a conventional routing algorithm shows that the proposed enhancement requires less routing time while giving similar or better QoR. On average, a speedup of 35% is recorded for the proposed routing enhancement as compared to negotiation-based congestion-driven routing solutions. Finally, the speedup of the routing step leads to an overall reduction in the execution time of the back-end flow of 25%. |
| first_indexed | 2024-03-09T10:20:29Z |
| format | Article |
| id | doaj.art-a16ee230e57e4ab68d985591e3022cd2 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T10:20:29Z |
| publishDate | 2022-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-a16ee230e57e4ab68d985591e3022cd22023-12-01T22:05:36ZengMDPI AGElectronics2079-92922022-07-011114224010.3390/electronics11142240Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement LearningImran Baig0Umer Farooq1Department of Electrical and Computer Engineering, Dhofar University, Salalah 211, OmanSchool of Engineering, University of Sunderland, Sunderland SR6 0AA, UKOver the past few years, the computation capability of field-programmable gate arrays (FPGAs) has increased tremendously. This has led to the increase in the complexity of the designs implemented on FPGAs and to the time taken by the FPGA back-end flow. The FPGA back-end flow comprises of many steps, and routing is one of the most critical steps among them. Routing normally constitutes more than 50% of the total time taken by the back-end flow and an optimization at this step can lead to overall optimization of the back-end flow. In this work, we propose enhancements to the routing step by incorporating a reinforcement learning (RL)-based framework. In the proposed RL-based framework, we use the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>ϵ</mi></semantics></math></inline-formula>-greedy approach and customized reward functions to speed up the routing step while maintaining similar or better quality of results (QoR) as compared to the conventional negotiation-based congestion-driven routing solution. For experimentation, we use two sets of widely deployed, large heterogeneous benchmarks. Our results show that, for the RL-based framework, the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>ϵ</mi></semantics></math></inline-formula>-greedy greedy approach combined with a modified reward function gives better results as compared to purely greedy or exploratory approaches. Moreover, the incorporation of the proposed reward function in the RL-based framework and its comparison with a conventional routing algorithm shows that the proposed enhancement requires less routing time while giving similar or better QoR. On average, a speedup of 35% is recorded for the proposed routing enhancement as compared to negotiation-based congestion-driven routing solutions. Finally, the speedup of the routing step leads to an overall reduction in the execution time of the back-end flow of 25%.https://www.mdpi.com/2079-9292/11/14/2240FPGA back-end flowreinforcement learningrouting |
| spellingShingle | Imran Baig Umer Farooq Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning Electronics FPGA back-end flow reinforcement learning routing |
| title | Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning |
| title_full | Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning |
| title_fullStr | Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning |
| title_full_unstemmed | Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning |
| title_short | Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning |
| title_sort | efficient detailed routing for fpga back end flow using reinforcement learning |
| topic | FPGA back-end flow reinforcement learning routing |
| url | https://www.mdpi.com/2079-9292/11/14/2240 |
| work_keys_str_mv | AT imranbaig efficientdetailedroutingforfpgabackendflowusingreinforcementlearning AT umerfarooq efficientdetailedroutingforfpgabackendflowusingreinforcementlearning |