Charge trapping analysis in sputtered BixSe1-x based accumulation-mode FETs. II. Gate capacitance characteristics - Protyush Sahu; Jun-Yang Chen; Jian-Ping Wang (AIP Advances, 2021)
In this study, we extend the analyses done on sputtered BixSe1-x based accumulation mode FETs. Previously, we studied the basic electrical and leakage properties of these FET devices. We extend our analyses to obtain key parameters of the BixSe1-x (x = 0.44) film at various gate voltages. We start by extracting the sheet carrier density and bulk mobility for different gate voltages, using the Drude model with the previously obtained semi-empirical relationship between carrier concentration and bulk mobility for BixSe1-x. The change in sheet carrier density is a result of accumulation or depletion or majority carriers from the BixSe1-x/SiO2 interface, which show hysteretic behavior. This allows us to calculate the surface sheet carrier density and the quasi-static capacitance at various gate voltages. We use a simple capacitive model to separate the capacitance originating from the gate and the film bulk. The capacitance from the film bulk is due to the surface charge thickness and is directly dependent on the Debye length. From the change of capacitance, with respect to gate voltage, we were able to identify the characteristics of the conduction band edge and the bulk band gap/Dirac cone.