| Summary: | In this article, we propose a novel vertical TFET that benefits from dual doping-less tunneling junction. Due to the low on-state current of silicon-based TFETs, we employ a dual-source configuration and a high-k dielectric material in the oxide region. The performance assessment of our device is thoroughly investigated using the Silvaco ATLAS device simulator. By activating models such as trap-assisted tunneling and interface trap charge for all the simulations our obtained results are less-ideal but closer to the experimental expectations. We also investigate the impact of Yttrium-doped hafnium, a well-known negative capacitance material, on our device performance. Parameters such as <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">$59.9~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$I_{on}/I_{off}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math notation="LaTeX">$2.95\times 10^{8}$ </tex-math></inline-formula> show that our Si-based device is a notable candidate for CMOS applications.
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