A Novel Vertical Si TFET With Dual Doping-Less Tunneling Junction: A Simulation Study Including Trap-Related Non-Idealities
In this article, we propose a novel vertical TFET that benefits from dual doping-less tunneling junction. Due to the low on-state current of silicon-based TFETs, we employ a dual-source configuration and a high-k dielectric material in the oxide region. The performance assessment of our device is th...
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10210567/ |
| _version_ | 1797743465989144576 |
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| author | Iman Chahardah Cherik Saeed Mohammadi |
| author_facet | Iman Chahardah Cherik Saeed Mohammadi |
| author_sort | Iman Chahardah Cherik |
| collection | DOAJ |
| description | In this article, we propose a novel vertical TFET that benefits from dual doping-less tunneling junction. Due to the low on-state current of silicon-based TFETs, we employ a dual-source configuration and a high-k dielectric material in the oxide region. The performance assessment of our device is thoroughly investigated using the Silvaco ATLAS device simulator. By activating models such as trap-assisted tunneling and interface trap charge for all the simulations our obtained results are less-ideal but closer to the experimental expectations. We also investigate the impact of Yttrium-doped hafnium, a well-known negative capacitance material, on our device performance. Parameters such as <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">$59.9~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$I_{on}/I_{off}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math notation="LaTeX">$2.95\times 10^{8}$ </tex-math></inline-formula> show that our Si-based device is a notable candidate for CMOS applications. |
| first_indexed | 2024-03-12T14:55:48Z |
| format | Article |
| id | doaj.art-a1f4dcb94a1e4901ab8d56be3555167a |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-12T14:55:48Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-a1f4dcb94a1e4901ab8d56be3555167a2023-08-14T23:00:26ZengIEEEIEEE Access2169-35362023-01-0111838818388610.1109/ACCESS.2023.330319810210567A Novel Vertical Si TFET With Dual Doping-Less Tunneling Junction: A Simulation Study Including Trap-Related Non-IdealitiesIman Chahardah Cherik0https://orcid.org/0000-0002-1858-1769Saeed Mohammadi1https://orcid.org/0000-0002-3143-1650Department of Electrical and Computer Engineering, Semnan University, Semnan, IranDepartment of Electrical and Computer Engineering, Semnan University, Semnan, IranIn this article, we propose a novel vertical TFET that benefits from dual doping-less tunneling junction. Due to the low on-state current of silicon-based TFETs, we employ a dual-source configuration and a high-k dielectric material in the oxide region. The performance assessment of our device is thoroughly investigated using the Silvaco ATLAS device simulator. By activating models such as trap-assisted tunneling and interface trap charge for all the simulations our obtained results are less-ideal but closer to the experimental expectations. We also investigate the impact of Yttrium-doped hafnium, a well-known negative capacitance material, on our device performance. Parameters such as <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">$59.9~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$I_{on}/I_{off}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math notation="LaTeX">$2.95\times 10^{8}$ </tex-math></inline-formula> show that our Si-based device is a notable candidate for CMOS applications.https://ieeexplore.ieee.org/document/10210567/Doping-lessnegative capacitancesubthreshold swingTFETtrap-assisted tunneling |
| spellingShingle | Iman Chahardah Cherik Saeed Mohammadi A Novel Vertical Si TFET With Dual Doping-Less Tunneling Junction: A Simulation Study Including Trap-Related Non-Idealities IEEE Access Doping-less negative capacitance subthreshold swing TFET trap-assisted tunneling |
| title | A Novel Vertical Si TFET With Dual Doping-Less Tunneling Junction: A Simulation Study Including Trap-Related Non-Idealities |
| title_full | A Novel Vertical Si TFET With Dual Doping-Less Tunneling Junction: A Simulation Study Including Trap-Related Non-Idealities |
| title_fullStr | A Novel Vertical Si TFET With Dual Doping-Less Tunneling Junction: A Simulation Study Including Trap-Related Non-Idealities |
| title_full_unstemmed | A Novel Vertical Si TFET With Dual Doping-Less Tunneling Junction: A Simulation Study Including Trap-Related Non-Idealities |
| title_short | A Novel Vertical Si TFET With Dual Doping-Less Tunneling Junction: A Simulation Study Including Trap-Related Non-Idealities |
| title_sort | novel vertical si tfet with dual doping less tunneling junction a simulation study including trap related non idealities |
| topic | Doping-less negative capacitance subthreshold swing TFET trap-assisted tunneling |
| url | https://ieeexplore.ieee.org/document/10210567/ |
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