TECHNOLOGY MAPPING TOOL FOR VLSI CAD
Technology mapping program implements a sequential circuit using the gates of a particular technology library. It is an integral component of any automated VLSI circuit design flow. The structure of the program for solving the technology mapping problem and formats of the source and result data are...
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| Format: | Article |
| Language: | Russian |
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The United Institute of Informatics Problems of the National Academy of Sciences of Belarus
2017-03-01
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| Series: | Informatika |
| Online Access: | https://inf.grid.by/jour/article/view/200 |
| _version_ | 1797877395136446464 |
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| author | D. I. Cheremisinov |
| author_facet | D. I. Cheremisinov |
| author_sort | D. I. Cheremisinov |
| collection | DOAJ |
| description | Technology mapping program implements a sequential circuit using the gates of a particular technology library. It is an integral component of any automated VLSI circuit design flow. The structure of the program for solving the technology mapping problem and formats of the source and result data are presented. Models of intermediate representations of the sequential circuit and their conversions are described. Technology mapping is a stage of logic synthesis and it is viewed as the transformation of a functional (i.e., algebraic) circuit specification into a gate (i.e., netlist) specification. The program is included as project operations in the VLSI CAD system for energy-saving logical synthesis developed in the United Institute of Informatics Problems of NAS of Belarus. |
| first_indexed | 2024-04-10T02:16:30Z |
| format | Article |
| id | doaj.art-a214e6ee0cef46e6aed29a9c5789c994 |
| institution | Directory Open Access Journal |
| issn | 1816-0301 |
| language | Russian |
| last_indexed | 2024-04-10T02:16:30Z |
| publishDate | 2017-03-01 |
| publisher | The United Institute of Informatics Problems of the National Academy of Sciences of Belarus |
| record_format | Article |
| series | Informatika |
| spelling | doaj.art-a214e6ee0cef46e6aed29a9c5789c9942023-03-13T08:32:18ZrusThe United Institute of Informatics Problems of the National Academy of Sciences of BelarusInformatika1816-03012017-03-0101(53)4452199TECHNOLOGY MAPPING TOOL FOR VLSI CADD. I. Cheremisinov0Объединенный институт проблем информатики НАН БеларусиTechnology mapping program implements a sequential circuit using the gates of a particular technology library. It is an integral component of any automated VLSI circuit design flow. The structure of the program for solving the technology mapping problem and formats of the source and result data are presented. Models of intermediate representations of the sequential circuit and their conversions are described. Technology mapping is a stage of logic synthesis and it is viewed as the transformation of a functional (i.e., algebraic) circuit specification into a gate (i.e., netlist) specification. The program is included as project operations in the VLSI CAD system for energy-saving logical synthesis developed in the United Institute of Informatics Problems of NAS of Belarus.https://inf.grid.by/jour/article/view/200 |
| spellingShingle | D. I. Cheremisinov TECHNOLOGY MAPPING TOOL FOR VLSI CAD Informatika |
| title | TECHNOLOGY MAPPING TOOL FOR VLSI CAD |
| title_full | TECHNOLOGY MAPPING TOOL FOR VLSI CAD |
| title_fullStr | TECHNOLOGY MAPPING TOOL FOR VLSI CAD |
| title_full_unstemmed | TECHNOLOGY MAPPING TOOL FOR VLSI CAD |
| title_short | TECHNOLOGY MAPPING TOOL FOR VLSI CAD |
| title_sort | technology mapping tool for vlsi cad |
| url | https://inf.grid.by/jour/article/view/200 |
| work_keys_str_mv | AT dicheremisinov technologymappingtoolforvlsicad |