Proposal of Global Strain Clocking Scheme for Majority Logic Gate
A stairs-type global strain clocking mechanism for nanomagnetic majority logic gate based on shape engineering of nanomagnets was designed in this paper. Reasonable size nanomagnets and proper strain clocking scheme ensure the computing architecture pipelined at room temperature. The optimal global...
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9076677/ |
| _version_ | 1828928615851491328 |
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| author | Yabo Chen Xiaokuo Yang Bo Wei Huanqing Cui Mingxu Song |
| author_facet | Yabo Chen Xiaokuo Yang Bo Wei Huanqing Cui Mingxu Song |
| author_sort | Yabo Chen |
| collection | DOAJ |
| description | A stairs-type global strain clocking mechanism for nanomagnetic majority logic gate based on shape engineering of nanomagnets was designed in this paper. Reasonable size nanomagnets and proper strain clocking scheme ensure the computing architecture pipelined at room temperature. The optimal global strain clocking scheme was obtained by investigating the impact of magnetic layer thickness and width on clocking period and strain magnitude. Encouragingly, for the global strain clocking, information transmission speed of majority logic gate is increased 1-2 times as against the local strain clocking scheme due to decreasing the number of start-ups during information transmission. While the energy dissipated per clock cycle of the global strain clocking scheme consumes 3-4 times less energy than that of local strain clocking scheme. Moreover, global clocking is used to control a nanomagnetic logic device(NMLD), in which case single device consisted of many nanomagnets can be treated as single nanomagnet. However, magnetization switching is error-prone in the presence of thermal noise at room temperature. Therefore, the proper structure parameters of the device are obtained at room temperature, in which case the error probability of the majority logic gate is 0.5% in theoretical simulation. These results provide essential guidance for the design of energy-efficient multiferroic nanomagnetic logic devices. |
| first_indexed | 2024-12-14T00:07:03Z |
| format | Article |
| id | doaj.art-a2555b1af83a4873b7da6154f44d58c6 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-14T00:07:03Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-a2555b1af83a4873b7da6154f44d58c62022-12-21T23:25:58ZengIEEEIEEE Access2169-35362020-01-018778027781010.1109/ACCESS.2020.29899309076677Proposal of Global Strain Clocking Scheme for Majority Logic GateYabo Chen0https://orcid.org/0000-0003-2751-0118Xiaokuo Yang1https://orcid.org/0000-0002-4956-4005Bo Wei2https://orcid.org/0000-0002-4953-3049Huanqing Cui3https://orcid.org/0000-0001-9935-0120Mingxu Song4https://orcid.org/0000-0002-7795-8773Department of Foundation, Air Force Engineering University, Xi’an, ChinaDepartment of Foundation, Air Force Engineering University, Xi’an, ChinaDepartment of Foundation, Air Force Engineering University, Xi’an, ChinaDepartment of Foundation, Air Force Engineering University, Xi’an, ChinaDepartment of Foundation, Air Force Engineering University, Xi’an, ChinaA stairs-type global strain clocking mechanism for nanomagnetic majority logic gate based on shape engineering of nanomagnets was designed in this paper. Reasonable size nanomagnets and proper strain clocking scheme ensure the computing architecture pipelined at room temperature. The optimal global strain clocking scheme was obtained by investigating the impact of magnetic layer thickness and width on clocking period and strain magnitude. Encouragingly, for the global strain clocking, information transmission speed of majority logic gate is increased 1-2 times as against the local strain clocking scheme due to decreasing the number of start-ups during information transmission. While the energy dissipated per clock cycle of the global strain clocking scheme consumes 3-4 times less energy than that of local strain clocking scheme. Moreover, global clocking is used to control a nanomagnetic logic device(NMLD), in which case single device consisted of many nanomagnets can be treated as single nanomagnet. However, magnetization switching is error-prone in the presence of thermal noise at room temperature. Therefore, the proper structure parameters of the device are obtained at room temperature, in which case the error probability of the majority logic gate is 0.5% in theoretical simulation. These results provide essential guidance for the design of energy-efficient multiferroic nanomagnetic logic devices.https://ieeexplore.ieee.org/document/9076677/Energy-efficientglobal strain clockingnanomagnetic logic device (NMLD)shape engineeringspintronics |
| spellingShingle | Yabo Chen Xiaokuo Yang Bo Wei Huanqing Cui Mingxu Song Proposal of Global Strain Clocking Scheme for Majority Logic Gate IEEE Access Energy-efficient global strain clocking nanomagnetic logic device (NMLD) shape engineering spintronics |
| title | Proposal of Global Strain Clocking Scheme for Majority Logic Gate |
| title_full | Proposal of Global Strain Clocking Scheme for Majority Logic Gate |
| title_fullStr | Proposal of Global Strain Clocking Scheme for Majority Logic Gate |
| title_full_unstemmed | Proposal of Global Strain Clocking Scheme for Majority Logic Gate |
| title_short | Proposal of Global Strain Clocking Scheme for Majority Logic Gate |
| title_sort | proposal of global strain clocking scheme for majority logic gate |
| topic | Energy-efficient global strain clocking nanomagnetic logic device (NMLD) shape engineering spintronics |
| url | https://ieeexplore.ieee.org/document/9076677/ |
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