Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell
This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SR...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Hindawi Limited
2023-01-01
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| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/2023/3371599 |
| _version_ | 1797785122786770944 |
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| author | Chokkakula Ganesh Fazal Noorbasha |
| author_facet | Chokkakula Ganesh Fazal Noorbasha |
| author_sort | Chokkakula Ganesh |
| collection | DOAJ |
| description | This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer. |
| first_indexed | 2024-03-13T00:49:35Z |
| format | Article |
| id | doaj.art-a2efca7c497e491aa62c90347152f6db |
| institution | Directory Open Access Journal |
| issn | 1563-5031 |
| language | English |
| last_indexed | 2024-03-13T00:49:35Z |
| publishDate | 2023-01-01 |
| publisher | Hindawi Limited |
| record_format | Article |
| series | Active and Passive Electronic Components |
| spelling | doaj.art-a2efca7c497e491aa62c90347152f6db2023-07-08T00:00:14ZengHindawi LimitedActive and Passive Electronic Components1563-50312023-01-01202310.1155/2023/3371599Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM CellChokkakula Ganesh0Fazal Noorbasha1Department of Electronics and Communication EngineeringDepartment of Electronics and Communication EngineeringThis work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.http://dx.doi.org/10.1155/2023/3371599 |
| spellingShingle | Chokkakula Ganesh Fazal Noorbasha Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell Active and Passive Electronic Components |
| title | Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell |
| title_full | Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell |
| title_fullStr | Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell |
| title_full_unstemmed | Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell |
| title_short | Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell |
| title_sort | performance and stability analysis of built in self read and write assist 10t sram cell |
| url | http://dx.doi.org/10.1155/2023/3371599 |
| work_keys_str_mv | AT chokkakulaganesh performanceandstabilityanalysisofbuiltinselfreadandwriteassist10tsramcell AT fazalnoorbasha performanceandstabilityanalysisofbuiltinselfreadandwriteassist10tsramcell |