Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC
In this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be c...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-03-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/5/603 |
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| author | Pramod Kumar Meher Siew-Kei Lam Thambipillai Srikanthan Dong Hwan Kim Sang Yoon Park |
| author_facet | Pramod Kumar Meher Siew-Kei Lam Thambipillai Srikanthan Dong Hwan Kim Sang Yoon Park |
| author_sort | Pramod Kumar Meher |
| collection | DOAJ |
| description | In this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be configured for the computation of the DCT of any of the prescribed lengths such as 4, 8, 16, and 32. It is shown that matrix multiplication schemes involving fewer adders can be used to derive parallel architectures for 1D integer DCT of different lengths. A novel transposition buffer is designed to be used for the proposed 2D DCT architecture, which offers double the throughput without increasing the size of the transposition buffer. We determine the optimal pipeline locations in the proposed design through the precise estimation of propagation delays and the critical path so that the area-delay-product is optimized and all the output samples are obtained in the same cycle in spite of the recursive nature of the structure. Implementation results show that the proposed 2D integer DCT architectures provide significantly higher throughput per unit area than the existing designs for HEVC. |
| first_indexed | 2024-03-09T05:25:30Z |
| format | Article |
| id | doaj.art-a4406d45709449d0907f6fcad19e2310 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T05:25:30Z |
| publishDate | 2021-03-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-a4406d45709449d0907f6fcad19e23102023-12-03T12:37:14ZengMDPI AGElectronics2079-92922021-03-0110560310.3390/electronics10050603Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVCPramod Kumar Meher0Siew-Kei Lam1Thambipillai Srikanthan2Dong Hwan Kim3Sang Yoon Park4Sandhaan Labs Private Limited, Bhubaneswar 751016, Odisha, IndiaSchool of Computer Science and Engineering, Nanyang Technological University, Singapore 639798, SingaporeSchool of Computer Science and Engineering, Nanyang Technological University, Singapore 639798, SingaporeDepartment of Electronic Engineering, Myongji University, Yongin 17058, KoreaDepartment of Electronic Engineering, Myongji University, Yongin 17058, KoreaIn this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be configured for the computation of the DCT of any of the prescribed lengths such as 4, 8, 16, and 32. It is shown that matrix multiplication schemes involving fewer adders can be used to derive parallel architectures for 1D integer DCT of different lengths. A novel transposition buffer is designed to be used for the proposed 2D DCT architecture, which offers double the throughput without increasing the size of the transposition buffer. We determine the optimal pipeline locations in the proposed design through the precise estimation of propagation delays and the critical path so that the area-delay-product is optimized and all the output samples are obtained in the same cycle in spite of the recursive nature of the structure. Implementation results show that the proposed 2D integer DCT architectures provide significantly higher throughput per unit area than the existing designs for HEVC.https://www.mdpi.com/2079-9292/10/5/603discrete cosine transform (DCT)High Efficiency Video Coding (HEVC)H.265integer DCTvideo coding |
| spellingShingle | Pramod Kumar Meher Siew-Kei Lam Thambipillai Srikanthan Dong Hwan Kim Sang Yoon Park Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC Electronics discrete cosine transform (DCT) High Efficiency Video Coding (HEVC) H.265 integer DCT video coding |
| title | Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC |
| title_full | Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC |
| title_fullStr | Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC |
| title_full_unstemmed | Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC |
| title_short | Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC |
| title_sort | area time efficient two dimensional reconfigurable integer dct architecture for hevc |
| topic | discrete cosine transform (DCT) High Efficiency Video Coding (HEVC) H.265 integer DCT video coding |
| url | https://www.mdpi.com/2079-9292/10/5/603 |
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