Build Testbenches for Verification in Shift Register ICs using SystemVerilog
A testbench is built to verify a functionality of a shift register IC (Integrated Circuit) from stuck-at-faults, stuck-at-1 as well as stuck-at-0. The testbench is supported by components, i.e., generator, interface, driver, monitor, scoreboard, environment, test, and testbench top. The IC consists...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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Polish Academy of Sciences
2022-09-01
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| Series: | International Journal of Electronics and Telecommunications |
| Subjects: | |
| Online Access: | https://journals.pan.pl/Content/124273/PDF/21-3488-12094-1-PB.pdf |
| _version_ | 1811205837898645504 |
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| author | Widianto H.M. Chasrun Robert Lis |
| author_facet | Widianto H.M. Chasrun Robert Lis |
| author_sort | Widianto |
| collection | DOAJ |
| description | A testbench is built to verify a functionality of a shift register IC (Integrated Circuit) from stuck-at-faults, stuck-at-1 as well as stuck-at-0. The testbench is supported by components, i.e., generator, interface, driver, monitor, scoreboard, environment, test, and testbench top. The IC consists of sequential logic circuits of D-type flip-flops. The faults may occur at interconnects between the circuits inside the IC. In order to examine the functionality from the faults, both the testbench and the IC are designed using SystemVerilog and simulated using Questasim simulator. Simulation results show the faults may be detected by the testbench. Moreover, the detected faults may be indicated by error statements in transcript results of the simulator. |
| first_indexed | 2024-04-12T03:37:50Z |
| format | Article |
| id | doaj.art-a5aeebff8dff453180972b7700230d66 |
| institution | Directory Open Access Journal |
| issn | 2081-8491 2300-1933 |
| language | English |
| last_indexed | 2024-04-12T03:37:50Z |
| publishDate | 2022-09-01 |
| publisher | Polish Academy of Sciences |
| record_format | Article |
| series | International Journal of Electronics and Telecommunications |
| spelling | doaj.art-a5aeebff8dff453180972b7700230d662022-12-22T03:49:22ZengPolish Academy of SciencesInternational Journal of Electronics and Telecommunications2081-84912300-19332022-09-01vol. 68No 3619623https://doi.org/10.24425/ijet.2022.141281Build Testbenches for Verification in Shift Register ICs using SystemVerilogWidianto0H.M. Chasrun1Robert Lis2University of Muhammadiyah Malang, Department of Electrical Engineering, IndonesiaUniversity of Muhammadiyah Malang, Department of Electrical Engineering, IndonesiaWroclaw University of Science and Technology, PolandA testbench is built to verify a functionality of a shift register IC (Integrated Circuit) from stuck-at-faults, stuck-at-1 as well as stuck-at-0. The testbench is supported by components, i.e., generator, interface, driver, monitor, scoreboard, environment, test, and testbench top. The IC consists of sequential logic circuits of D-type flip-flops. The faults may occur at interconnects between the circuits inside the IC. In order to examine the functionality from the faults, both the testbench and the IC are designed using SystemVerilog and simulated using Questasim simulator. Simulation results show the faults may be detected by the testbench. Moreover, the detected faults may be indicated by error statements in transcript results of the simulator.https://journals.pan.pl/Content/124273/PDF/21-3488-12094-1-PB.pdftestbenchverificationshift register icstuck-atfaultssystemverilog |
| spellingShingle | Widianto H.M. Chasrun Robert Lis Build Testbenches for Verification in Shift Register ICs using SystemVerilog International Journal of Electronics and Telecommunications testbench verification shift register ic stuck-atfaults systemverilog |
| title | Build Testbenches for Verification in Shift Register ICs using SystemVerilog |
| title_full | Build Testbenches for Verification in Shift Register ICs using SystemVerilog |
| title_fullStr | Build Testbenches for Verification in Shift Register ICs using SystemVerilog |
| title_full_unstemmed | Build Testbenches for Verification in Shift Register ICs using SystemVerilog |
| title_short | Build Testbenches for Verification in Shift Register ICs using SystemVerilog |
| title_sort | build testbenches for verification in shift register ics using systemverilog |
| topic | testbench verification shift register ic stuck-atfaults systemverilog |
| url | https://journals.pan.pl/Content/124273/PDF/21-3488-12094-1-PB.pdf |
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