A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications
A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-...
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| Format: | Article |
| Language: | English |
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MDPI AG
2020-03-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/4/562 |
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| author | Dong-Myeong Kim Dongmin Kim Hang-Geun Jeong Donggu Im |
| author_facet | Dong-Myeong Kim Dongmin Kim Hang-Geun Jeong Donggu Im |
| author_sort | Dong-Myeong Kim |
| collection | DOAJ |
| description | A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (<i>V<sub>th</sub></i>) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load <i>R<sub>opt</sub></i>, resulting in maximum output power with peak power added efficiency (<i>PAE</i>). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × <i>V<sub>DD</sub></i>, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show <i>R<sub>opt</sub></i> of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (<i>P<sub>sat</sub></i>) of +6.1 dBm and a peak <i>PAE</i> of 41.1% under a 100 Ω load impedance condition, a <i>P<sub>sat</sub></i> of +4.5 dBm and a peak <i>PAE</i> of 44.3% under a 50 Ω load impedance condition, and a <i>P<sub>sat</sub></i> of +5.2 dBm and a peak <i>PAE</i> of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration. |
| first_indexed | 2024-03-11T10:11:06Z |
| format | Article |
| id | doaj.art-a640770230024fbbbc256709881071e1 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-11T10:11:06Z |
| publishDate | 2020-03-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-a640770230024fbbbc256709881071e12023-11-16T14:30:37ZengMDPI AGElectronics2079-92922020-03-019456210.3390/electronics9040562A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless CommunicationsDong-Myeong Kim0Dongmin Kim1Hang-Geun Jeong2Donggu Im3Division of Electronic Engineering, Jeonbuk National University, Jollabuk-do 561-756, KoreaDivision of Electronic Engineering, Jeonbuk National University, Jollabuk-do 561-756, KoreaDivision of Electronic Engineering, Jeonbuk National University, Jollabuk-do 561-756, KoreaDivision of Electronic Engineering, Jeonbuk National University, Jollabuk-do 561-756, KoreaA reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (<i>V<sub>th</sub></i>) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load <i>R<sub>opt</sub></i>, resulting in maximum output power with peak power added efficiency (<i>PAE</i>). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × <i>V<sub>DD</sub></i>, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show <i>R<sub>opt</sub></i> of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (<i>P<sub>sat</sub></i>) of +6.1 dBm and a peak <i>PAE</i> of 41.1% under a 100 Ω load impedance condition, a <i>P<sub>sat</sub></i> of +4.5 dBm and a peak <i>PAE</i> of 44.3% under a 50 Ω load impedance condition, and a <i>P<sub>sat</sub></i> of +5.2 dBm and a peak <i>PAE</i> of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration.https://www.mdpi.com/2079-9292/9/4/562antenna impedance mismatchbreakdowncascode inverterCMOSimpedance coveragepower added efficiency |
| spellingShingle | Dong-Myeong Kim Dongmin Kim Hang-Geun Jeong Donggu Im A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications Electronics antenna impedance mismatch breakdown cascode inverter CMOS impedance coverage power added efficiency |
| title | A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications |
| title_full | A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications |
| title_fullStr | A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications |
| title_full_unstemmed | A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications |
| title_short | A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications |
| title_sort | reconfigurable cmos inverter based stacked power amplifier with antenna impedance mismatch compensation for low power short range wireless communications |
| topic | antenna impedance mismatch breakdown cascode inverter CMOS impedance coverage power added efficiency |
| url | https://www.mdpi.com/2079-9292/9/4/562 |
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