Delta Multi-Stage Interconnection Networks for Scalable Wireless On-Chip Communication

The Network-on-Chip (NoC) paradigm emerged as a viable solution to provide an efficient and scalable communication backbone for next-generation Multiprocessor Systems-on-Chip. As the number of integrated cores keeps growing, alternatives to the traditional multi-hop wired NoCs, such as wireless Netw...

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Bibliographic Details
Main Authors: Sirine Mnejja, Yassine Aydi, Mohamed Abid, Salvatore Monteleone, Vincenzo Catania, Maurizio Palesi, Davide Patti
Format: Article
Language:English
Published: MDPI AG 2020-05-01
Series:Electronics
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Online Access:https://www.mdpi.com/2079-9292/9/6/913
Description
Summary:The Network-on-Chip (NoC) paradigm emerged as a viable solution to provide an efficient and scalable communication backbone for next-generation Multiprocessor Systems-on-Chip. As the number of integrated cores keeps growing, alternatives to the traditional multi-hop wired NoCs, such as wireless Networks-on-Chip (WiNoCs), have been proposed to provide long-range communications in a single hop. In this work, we propose and analyze the integration of the Delta Multistage Interconnection Network (MINs) as a backbone for wireless-enabled NoCs. After extending the well-known Noxim platform to implement a cycle-accurate model of a wireless Delta MIN, we perform a comprehensive set of SystemC simulations to analyze how wireless-augmented Delta MINs can potentially lead to an improvement in both average delay and saturation. Further, we compare the results obtained with traditional mesh-based topologies, reporting energy profiles that show an overall energy cost reduced on both wired/wireless scenarios.
ISSN:2079-9292