Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications
This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be tra...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-07-01
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| Series: | Nanomaterials |
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| Online Access: | https://www.mdpi.com/2079-4991/11/7/1773 |
| _version_ | 1797526471434043392 |
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| author | Md. Hasan Raza Ansari Udaya Mohanan Kannan Seongjae Cho |
| author_facet | Md. Hasan Raza Ansari Udaya Mohanan Kannan Seongjae Cho |
| author_sort | Md. Hasan Raza Ansari |
| collection | DOAJ |
| description | This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware. |
| first_indexed | 2024-03-10T09:30:45Z |
| format | Article |
| id | doaj.art-a854bc8e79ce4485879e16032563e758 |
| institution | Directory Open Access Journal |
| issn | 2079-4991 |
| language | English |
| last_indexed | 2024-03-10T09:30:45Z |
| publishDate | 2021-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Nanomaterials |
| spelling | doaj.art-a854bc8e79ce4485879e16032563e7582023-11-22T04:33:42ZengMDPI AGNanomaterials2079-49912021-07-01117177310.3390/nano11071773Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic ApplicationsMd. Hasan Raza Ansari0Udaya Mohanan Kannan1Seongjae Cho2Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, KoreaGraduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, KoreaGraduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, KoreaThis work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.https://www.mdpi.com/2079-4991/11/7/1773short-term potentiation (STP)long-term potentiation (LTP)charge-trap synaptic transistorband-to-band tunnelingpattern recognitionneural network |
| spellingShingle | Md. Hasan Raza Ansari Udaya Mohanan Kannan Seongjae Cho Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications Nanomaterials short-term potentiation (STP) long-term potentiation (LTP) charge-trap synaptic transistor band-to-band tunneling pattern recognition neural network |
| title | Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications |
| title_full | Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications |
| title_fullStr | Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications |
| title_full_unstemmed | Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications |
| title_short | Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications |
| title_sort | core shell dual gate nanowire charge trap memory for synaptic operations for neuromorphic applications |
| topic | short-term potentiation (STP) long-term potentiation (LTP) charge-trap synaptic transistor band-to-band tunneling pattern recognition neural network |
| url | https://www.mdpi.com/2079-4991/11/7/1773 |
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