Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application
This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration,...
| Main Authors: | , , , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9200325/ |
| _version_ | 1811274101872918528 |
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| author | Yuanjun Cen Wei Feng Ping Yang Hua Fan Yongkai Li Yi Niu Zhikai Liao Xu Qi Bo Wang Yan Ran Wei Li Quanyuan Feng Hadi Heidari |
| author_facet | Yuanjun Cen Wei Feng Ping Yang Hua Fan Yongkai Li Yi Niu Zhikai Liao Xu Qi Bo Wang Yan Ran Wei Li Quanyuan Feng Hadi Heidari |
| author_sort | Yuanjun Cen |
| collection | DOAJ |
| description | This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a <inline-formula> <tex-math notation="LaTeX">$0.6~\mu m$ </tex-math></inline-formula> standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm <inline-formula> <tex-math notation="LaTeX">$\times6.6$ </tex-math></inline-formula>mm. As for single channel SAR ADC, the area is 0.9mm <inline-formula> <tex-math notation="LaTeX">$\times2.0$ </tex-math></inline-formula>mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step. |
| first_indexed | 2024-04-12T23:12:59Z |
| format | Article |
| id | doaj.art-a8e7e2157fb6419794952ca172f8c603 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-12T23:12:59Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-a8e7e2157fb6419794952ca172f8c6032022-12-22T03:12:46ZengIEEEIEEE Access2169-35362020-01-01817523017524310.1109/ACCESS.2020.30248079200325Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics ApplicationYuanjun Cen0https://orcid.org/0000-0002-9028-8241Wei Feng1https://orcid.org/0000-0001-8507-7901Ping Yang2https://orcid.org/0000-0001-5016-4618Hua Fan3https://orcid.org/0000-0001-7629-2183Yongkai Li4https://orcid.org/0000-0003-3415-6954Yi Niu5https://orcid.org/0000-0003-2482-3514Zhikai Liao6https://orcid.org/0000-0001-9455-6568Xu Qi7Bo Wang8https://orcid.org/0000-0002-4879-0545Yan Ran9https://orcid.org/0000-0002-7455-7026Wei Li10https://orcid.org/0000-0002-6056-4989Quanyuan Feng11https://orcid.org/0000-0003-4139-2015Hadi Heidari12https://orcid.org/0000-0001-8412-8164School of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, ChinaChengdu Sino Microelectronics Technology Company Ltd., Chengdu, ChinaChengdu Sino Microelectronics Technology Company Ltd., Chengdu, ChinaSchool of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, ChinaChengdu Sino Microelectronics Technology Company Ltd., Chengdu, ChinaChengdu Sino Microelectronics Technology Company Ltd., Chengdu, ChinaChengdu Sino Microelectronics Technology Company Ltd., Chengdu, ChinaChengdu Sino Microelectronics Technology Company Ltd., Chengdu, ChinaChengdu Sino Microelectronics Technology Company Ltd., Chengdu, ChinaChengdu Sino Microelectronics Technology Company Ltd., Chengdu, ChinaSchool of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, ChinaSchool of Information Science and Technology, Southwest Jiaotong University, Chengdu, ChinaSchool of Engineering, University of Glasgow, Glasgow, U.KThis paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a <inline-formula> <tex-math notation="LaTeX">$0.6~\mu m$ </tex-math></inline-formula> standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm <inline-formula> <tex-math notation="LaTeX">$\times6.6$ </tex-math></inline-formula>mm. As for single channel SAR ADC, the area is 0.9mm <inline-formula> <tex-math notation="LaTeX">$\times2.0$ </tex-math></inline-formula>mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.https://ieeexplore.ieee.org/document/9200325/Segmented capacitor arraySAR ADClinearity errorcalibration |
| spellingShingle | Yuanjun Cen Wei Feng Ping Yang Hua Fan Yongkai Li Yi Niu Zhikai Liao Xu Qi Bo Wang Yan Ran Wei Li Quanyuan Feng Hadi Heidari Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application IEEE Access Segmented capacitor array SAR ADC linearity error calibration |
| title | Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application |
| title_full | Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application |
| title_fullStr | Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application |
| title_full_unstemmed | Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application |
| title_short | Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application |
| title_sort | design of capacitor array in 16 bit ultra high precision sar adc for the wearable electronics application |
| topic | Segmented capacitor array SAR ADC linearity error calibration |
| url | https://ieeexplore.ieee.org/document/9200325/ |
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