Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA

Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA

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A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR) of 256 with a sampling frequency of 20.48 M...

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Bibliographic Details
Main Authors: Khalid Khaleel Mohammed, Mohammed Idrees Dawod
Format: Article
Language:English
Published: Tikrit University 2022-03-01
Series:Tikrit Journal of Engineering Sciences
Subjects:
Sigma-Delta modulation
Decimation filter
A/D conversion
Oversampling
FPGA
VHDL
Online Access:https://tj-es.com/ojs/index.php/tjes/article/view/293

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https://tj-es.com/ojs/index.php/tjes/article/view/293

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