Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience
Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2019-01-01
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| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9268/9/1/5 |
| _version_ | 1798034135921459200 |
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| author | Mini Jayakrishnan Alan Chang Tony Tae-Hyoung Kim |
| author_facet | Mini Jayakrishnan Alan Chang Tony Tae-Hyoung Kim |
| author_sort | Mini Jayakrishnan |
| collection | DOAJ |
| description | Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively. |
| first_indexed | 2024-04-11T20:40:03Z |
| format | Article |
| id | doaj.art-acbd5a3d25d14c2589ea0779fed94a1e |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-11T20:40:03Z |
| publishDate | 2019-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-acbd5a3d25d14c2589ea0779fed94a1e2022-12-22T04:04:15ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682019-01-0191510.3390/jlpea9010005jlpea9010005Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error ResilienceMini Jayakrishnan0Alan Chang1Tony Tae-Hyoung Kim2VIRTUS, IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, SingaporeNXP Semiconductors Singapore Pte Ltd, 1 Fusionopolis Walk, #12-01/02 South Tower, Solaris, Singapore 138628, SingaporeVIRTUS, IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, SingaporeEnergy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively.https://www.mdpi.com/2079-9268/9/1/5better than worst case designerror toleranceslack re-distributiontime borrowing |
| spellingShingle | Mini Jayakrishnan Alan Chang Tony Tae-Hyoung Kim Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience Journal of Low Power Electronics and Applications better than worst case design error tolerance slack re-distribution time borrowing |
| title | Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience |
| title_full | Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience |
| title_fullStr | Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience |
| title_full_unstemmed | Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience |
| title_short | Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience |
| title_sort | power and area efficient clock stretching and critical path reshaping for error resilience |
| topic | better than worst case design error tolerance slack re-distribution time borrowing |
| url | https://www.mdpi.com/2079-9268/9/1/5 |
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