Test Generation for Digital Hardware Based on High-Level Models
Hardware testing is a process aimed at detecting manufacturing faults in integrated circuits. To measure test quality, two main metrics are in use: fault detection abilities (fault coverage) and test application time (test length). Many algorithms have been suggested for test generation; however, no...
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Ivannikov Institute for System Programming of the Russian Academy of Sciences
2018-10-01
|
| Series: | Труды Института системного программирования РАН |
| Subjects: | |
| Online Access: | https://ispranproceedings.elpub.ru/jour/article/view/325 |
| _version_ | 1818389606199984128 |
|---|---|
| author | M. M. Chupilko A. S. Kamkin M. S. Lebedev S. A. Smolov |
| author_facet | M. M. Chupilko A. S. Kamkin M. S. Lebedev S. A. Smolov |
| author_sort | M. M. Chupilko |
| collection | DOAJ |
| description | Hardware testing is a process aimed at detecting manufacturing faults in integrated circuits. To measure test quality, two main metrics are in use: fault detection abilities (fault coverage) and test application time (test length). Many algorithms have been suggested for test generation; however, no scalable solution exists. In this paper, we analyze applicability of functional tests generated from high-level models for low-level manufacturing testing. A particular test generation method is considered. The input information is an HDL description. The key steps of the method are system model construction and coverage model construction. Both models are automatically extracted from the given description. The system model is a representation of the design in the form of high-level decision diagrams. The coverage model is a set of LTL formulae defining reachability conditions for the transitions of the extended finite state machine. The models are translated into the input format of a model checker. For each coverage model formula the model checker generates a counterexample, i.e. an execution that violates the formula (makes the corresponding transition to fire). The approach is intended for covering of all possible execution paths of the input HDL description and detecting dead code. Experimental comparison with the existing analogues has shown that it produces shorter tests, but they achieve lower stuck-at fault coverage comparing with the dedicated approach. An improvement has been proposed to overcome the issue. |
| first_indexed | 2024-12-14T04:44:24Z |
| format | Article |
| id | doaj.art-ae31f53688d8405d8aa9f9eb5848aa0d |
| institution | Directory Open Access Journal |
| issn | 2079-8156 2220-6426 |
| language | English |
| last_indexed | 2024-12-14T04:44:24Z |
| publishDate | 2018-10-01 |
| publisher | Ivannikov Institute for System Programming of the Russian Academy of Sciences |
| record_format | Article |
| series | Труды Института системного программирования РАН |
| spelling | doaj.art-ae31f53688d8405d8aa9f9eb5848aa0d2022-12-21T23:16:44ZengIvannikov Institute for System Programming of the Russian Academy of SciencesТруды Института системного программирования РАН2079-81562220-64262018-10-0129424725610.15514/ISPRAS-2017-29(4)-16325Test Generation for Digital Hardware Based on High-Level ModelsM. M. Chupilko0A. S. Kamkin1M. S. Lebedev2S. A. Smolov3Институт системного программирования РАНИнститут системного программирования РАН; Московский государственный университет им. М.В. Ломоносова; Московский физико-технический институтИнститут системного программирования РАНИнститут системного программирования РАНHardware testing is a process aimed at detecting manufacturing faults in integrated circuits. To measure test quality, two main metrics are in use: fault detection abilities (fault coverage) and test application time (test length). Many algorithms have been suggested for test generation; however, no scalable solution exists. In this paper, we analyze applicability of functional tests generated from high-level models for low-level manufacturing testing. A particular test generation method is considered. The input information is an HDL description. The key steps of the method are system model construction and coverage model construction. Both models are automatically extracted from the given description. The system model is a representation of the design in the form of high-level decision diagrams. The coverage model is a set of LTL formulae defining reachability conditions for the transitions of the extended finite state machine. The models are translated into the input format of a model checker. For each coverage model formula the model checker generates a counterexample, i.e. an execution that violates the formula (makes the corresponding transition to fire). The approach is intended for covering of all possible execution paths of the input HDL description and detecting dead code. Experimental comparison with the existing analogues has shown that it produces shorter tests, but they achieve lower stuck-at fault coverage comparing with the dedicated approach. An improvement has been proposed to overcome the issue.https://ispranproceedings.elpub.ru/jour/article/view/325цифровая аппаратураязык описания аппаратурыпроизводственное тестированиеконстантная ошибкавысокоуровневая решающая диаграммарасширенный конечный автоматпроверка моделидерево распространения |
| spellingShingle | M. M. Chupilko A. S. Kamkin M. S. Lebedev S. A. Smolov Test Generation for Digital Hardware Based on High-Level Models Труды Института системного программирования РАН цифровая аппаратура язык описания аппаратуры производственное тестирование константная ошибка высокоуровневая решающая диаграмма расширенный конечный автомат проверка модели дерево распространения |
| title | Test Generation for Digital Hardware Based on High-Level Models |
| title_full | Test Generation for Digital Hardware Based on High-Level Models |
| title_fullStr | Test Generation for Digital Hardware Based on High-Level Models |
| title_full_unstemmed | Test Generation for Digital Hardware Based on High-Level Models |
| title_short | Test Generation for Digital Hardware Based on High-Level Models |
| title_sort | test generation for digital hardware based on high level models |
| topic | цифровая аппаратура язык описания аппаратуры производственное тестирование константная ошибка высокоуровневая решающая диаграмма расширенный конечный автомат проверка модели дерево распространения |
| url | https://ispranproceedings.elpub.ru/jour/article/view/325 |
| work_keys_str_mv | AT mmchupilko testgenerationfordigitalhardwarebasedonhighlevelmodels AT askamkin testgenerationfordigitalhardwarebasedonhighlevelmodels AT mslebedev testgenerationfordigitalhardwarebasedonhighlevelmodels AT sasmolov testgenerationfordigitalhardwarebasedonhighlevelmodels |