An analog‐to‐digital converter calibration algorithm with clock jitter compensation based on bidirectional long‐short‐time‐memory
Abstract This letter proposes a bidirectional long‐short‐time‐memory (bi‐LSTM)‐based analog‐to‐digital converter (ADC) background calibration method with a clock jitter compensation function. Different from traditional calibration algorithms, the proposed algorithm utilizes the sequence property of...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2022-09-01
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| Series: | Electronics Letters |
| Online Access: | https://doi.org/10.1049/ell2.12598 |
| Summary: | Abstract This letter proposes a bidirectional long‐short‐time‐memory (bi‐LSTM)‐based analog‐to‐digital converter (ADC) background calibration method with a clock jitter compensation function. Different from traditional calibration algorithms, the proposed algorithm utilizes the sequence property of the signal by introducing an LSTM network. The network contains three parts, including a linear layer for input encoding, a refine layer for sequence processing, and a linear layer for output decoding. Two ADCs are used to train the network, one of which is the target to be calibrated, that is, a high‐speed high‐resolution ADC, and the other is a low‐speed ultra‐high‐resolution ADC producing the ideal signal. After the training stage, the network can be used as a postprocessor for the target ADC to compensate for the systemic errors and clock jitter, simultaneously. In the experiments, the proposed method is used to calibrate an ADC12D1600RFIUT, realizing the improvement of signal‐to‐noise distortion ratio (SNDR) from 43.41 to 66.82 dB and SFDR from 56.95 to 98.93 dB. |
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| ISSN: | 0013-5194 1350-911X |