Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate
To allow the use of molybdenum disulfide (MoS<sub>2</sub>) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS<sub>2</sub> transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is present...
| Main Authors: | , , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2019-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8686079/ |