Scalable and compact photonic neural chip with low learning-capability-loss
Photonic computation has garnered huge attention due to its great potential to accelerate artificial neural network tasks at much higher clock rate to digital electronic alternatives. Especially, reconfigurable photonic processor consisting of Mach–Zehnder interferometer (MZI) mesh is promising for...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
De Gruyter
2021-12-01
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| Series: | Nanophotonics |
| Subjects: | |
| Online Access: | https://doi.org/10.1515/nanoph-2021-0521 |
| _version_ | 1797947979746770944 |
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| author | Tian Ye Zhao Yang Liu Shengping Li Qiang Wang Wei Feng Junbo Guo Jin |
| author_facet | Tian Ye Zhao Yang Liu Shengping Li Qiang Wang Wei Feng Junbo Guo Jin |
| author_sort | Tian Ye |
| collection | DOAJ |
| description | Photonic computation has garnered huge attention due to its great potential to accelerate artificial neural network tasks at much higher clock rate to digital electronic alternatives. Especially, reconfigurable photonic processor consisting of Mach–Zehnder interferometer (MZI) mesh is promising for photonic matrix multiplier. It is desired to implement high-radix MZI mesh to boost the computation capability. Conventionally, three cascaded MZI meshes (two universal N × N unitary MZI mesh and one diagonal MZI mesh) are needed to express N × N weight matrix with O(N
2) MZIs requirements, which limits scalability seriously. Here, we propose a photonic matrix architecture using the real-part of one nonuniversal N × N unitary MZI mesh to represent the real-value matrix. In the applications like photonic neural network, it probable reduces the required MZIs to O(Nlog2 N) level while pay low cost on learning capability loss. Experimentally, we implement a 4 × 4 photonic neural chip and benchmark its performance in convolutional neural network for handwriting recognition task. Low learning-capability-loss is observed in our 4 × 4 chip compared to its counterpart based on conventional architecture using O(N
2) MZIs. While regarding the optical loss, chip size, power consumption, encoding error, our architecture exhibits all-round superiority. |
| first_indexed | 2024-04-10T21:35:14Z |
| format | Article |
| id | doaj.art-b0b8ed4f432b49888115d516c3115742 |
| institution | Directory Open Access Journal |
| issn | 2192-8614 |
| language | English |
| last_indexed | 2024-04-10T21:35:14Z |
| publishDate | 2021-12-01 |
| publisher | De Gruyter |
| record_format | Article |
| series | Nanophotonics |
| spelling | doaj.art-b0b8ed4f432b49888115d516c31157422023-01-19T12:46:58ZengDe GruyterNanophotonics2192-86142021-12-0111232934410.1515/nanoph-2021-0521Scalable and compact photonic neural chip with low learning-capability-lossTian Ye0Zhao Yang1Liu Shengping2Li Qiang3Wang Wei4Feng Junbo5Guo Jin6Chongqing United Microelectronics Center (CUMEC), No. 20 Xiyuannan Road, Chongqing100290, ChinaChongqing United Microelectronics Center (CUMEC), No. 20 Xiyuannan Road, Chongqing100290, ChinaChongqing United Microelectronics Center (CUMEC), No. 20 Xiyuannan Road, Chongqing100290, ChinaChongqing United Microelectronics Center (CUMEC), No. 20 Xiyuannan Road, Chongqing100290, ChinaChongqing United Microelectronics Center (CUMEC), No. 20 Xiyuannan Road, Chongqing100290, ChinaChongqing United Microelectronics Center (CUMEC), No. 20 Xiyuannan Road, Chongqing100290, ChinaChongqing United Microelectronics Center (CUMEC), No. 20 Xiyuannan Road, Chongqing100290, ChinaPhotonic computation has garnered huge attention due to its great potential to accelerate artificial neural network tasks at much higher clock rate to digital electronic alternatives. Especially, reconfigurable photonic processor consisting of Mach–Zehnder interferometer (MZI) mesh is promising for photonic matrix multiplier. It is desired to implement high-radix MZI mesh to boost the computation capability. Conventionally, three cascaded MZI meshes (two universal N × N unitary MZI mesh and one diagonal MZI mesh) are needed to express N × N weight matrix with O(N 2) MZIs requirements, which limits scalability seriously. Here, we propose a photonic matrix architecture using the real-part of one nonuniversal N × N unitary MZI mesh to represent the real-value matrix. In the applications like photonic neural network, it probable reduces the required MZIs to O(Nlog2 N) level while pay low cost on learning capability loss. Experimentally, we implement a 4 × 4 photonic neural chip and benchmark its performance in convolutional neural network for handwriting recognition task. Low learning-capability-loss is observed in our 4 × 4 chip compared to its counterpart based on conventional architecture using O(N 2) MZIs. While regarding the optical loss, chip size, power consumption, encoding error, our architecture exhibits all-round superiority.https://doi.org/10.1515/nanoph-2021-0521neural networkphotonic computationsilicon photonics |
| spellingShingle | Tian Ye Zhao Yang Liu Shengping Li Qiang Wang Wei Feng Junbo Guo Jin Scalable and compact photonic neural chip with low learning-capability-loss Nanophotonics neural network photonic computation silicon photonics |
| title | Scalable and compact photonic neural chip with low learning-capability-loss |
| title_full | Scalable and compact photonic neural chip with low learning-capability-loss |
| title_fullStr | Scalable and compact photonic neural chip with low learning-capability-loss |
| title_full_unstemmed | Scalable and compact photonic neural chip with low learning-capability-loss |
| title_short | Scalable and compact photonic neural chip with low learning-capability-loss |
| title_sort | scalable and compact photonic neural chip with low learning capability loss |
| topic | neural network photonic computation silicon photonics |
| url | https://doi.org/10.1515/nanoph-2021-0521 |
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