VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems

Hybrid precoding, a combination of radio frequency (RF) beamforming and digital precoding, has been investigated intensively these days for millimeter wave (mmWave) communication systems employing large antenna arrays. The key problem is constructing beamforming and precoding matrices for the RF bea...

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Main Authors: Kuan-Ting Chen, Yin-Tsung Hwang, Yen-Chang Liao
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/8737678/
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author Kuan-Ting Chen
Yin-Tsung Hwang
Yen-Chang Liao
author_facet Kuan-Ting Chen
Yin-Tsung Hwang
Yen-Chang Liao
author_sort Kuan-Ting Chen
collection DOAJ
description Hybrid precoding, a combination of radio frequency (RF) beamforming and digital precoding, has been investigated intensively these days for millimeter wave (mmWave) communication systems employing large antenna arrays. The key problem is constructing beamforming and precoding matrices for the RF beamformer and the digital baseband, respectively, based on the channel matrix decomposition result. This paper presents a new computing algorithm to achieve the matrix decomposition efficiently without compromising the performance. The algorithm computes beamforming (steering) and precoding matrices in separate phases to alleviate the computing overheads of iterative matrix updates. This measure also creates the computing parallelism to facilitate efficient hardware implementation. A novel computing scheme based on QR decomposition and blockwise inversion techniques is also developed to tackle the most critical least square solution module. This leads to a computing complexity reduction by a factor of 0.3 N when compared with the popular orthogonal matching pursuit (OMP) scheme, where N is the antenna array size. The simulation results indicate the percentage of choosing correct steering vectors is 90%, which is as good as the OMP scheme can achieve. A hardware accelerator design of the proposed scheme is developed by using a TSMC 40 nm CLN40G technology. The design, with a gate count of 419.3 k, can operate up to 333 MHz with a power consumption of 267.1 mW. This suggests a throughput rate of processing 10.4 M channel matrices per second. The core size is merely 0.58mm<sup>2</sup> while the entire die size including I/O pads is 2.26mm<sup>2</sup>.
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spelling doaj.art-b0cdd54be9b14232b6203520e9d504932022-12-21T22:25:34ZengIEEEIEEE Access2169-35362019-01-017859258593610.1109/ACCESS.2019.29232518737678VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO SystemsKuan-Ting Chen0Yin-Tsung Hwang1https://orcid.org/0000-0001-9233-0477Yen-Chang Liao2Department of Electrical Engineering, National Chung Hsing University, Taichung, TaiwanDepartment of Electrical Engineering, National Chung Hsing University, Taichung, TaiwanDivision of Digital IC Design, Ilitek Corporation, Hsinchu, TaiwanHybrid precoding, a combination of radio frequency (RF) beamforming and digital precoding, has been investigated intensively these days for millimeter wave (mmWave) communication systems employing large antenna arrays. The key problem is constructing beamforming and precoding matrices for the RF beamformer and the digital baseband, respectively, based on the channel matrix decomposition result. This paper presents a new computing algorithm to achieve the matrix decomposition efficiently without compromising the performance. The algorithm computes beamforming (steering) and precoding matrices in separate phases to alleviate the computing overheads of iterative matrix updates. This measure also creates the computing parallelism to facilitate efficient hardware implementation. A novel computing scheme based on QR decomposition and blockwise inversion techniques is also developed to tackle the most critical least square solution module. This leads to a computing complexity reduction by a factor of 0.3 N when compared with the popular orthogonal matching pursuit (OMP) scheme, where N is the antenna array size. The simulation results indicate the percentage of choosing correct steering vectors is 90%, which is as good as the OMP scheme can achieve. A hardware accelerator design of the proposed scheme is developed by using a TSMC 40 nm CLN40G technology. The design, with a gate count of 419.3 k, can operate up to 333 MHz with a power consumption of 267.1 mW. This suggests a throughput rate of processing 10.4 M channel matrices per second. The core size is merely 0.58mm<sup>2</sup> while the entire die size including I/O pads is 2.26mm<sup>2</sup>.https://ieeexplore.ieee.org/document/8737678/Multiple-input multiple-outputhybrid precodingarray beamformingmillimeter waveorthogonal matching pursuitQR-decomposition
spellingShingle Kuan-Ting Chen
Yin-Tsung Hwang
Yen-Chang Liao
VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems
IEEE Access
Multiple-input multiple-output
hybrid precoding
array beamforming
millimeter wave
orthogonal matching pursuit
QR-decomposition
title VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems
title_full VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems
title_fullStr VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems
title_full_unstemmed VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems
title_short VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems
title_sort vlsi design of a high throughput hybrid precoding processor for wireless mimo systems
topic Multiple-input multiple-output
hybrid precoding
array beamforming
millimeter wave
orthogonal matching pursuit
QR-decomposition
url https://ieeexplore.ieee.org/document/8737678/
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