Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition
The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achiev...
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| Format: | Article |
| Language: | English |
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D. G. Pylarinos
2023-02-01
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| Series: | Engineering, Technology & Applied Science Research |
| Subjects: | |
| Online Access: | https://etasr.com/index.php/ETASR/article/view/5567 |
| _version_ | 1811170961192386560 |
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| author | M. Kavitha S. Akhila Anand Kannan |
| author_facet | M. Kavitha S. Akhila Anand Kannan |
| author_sort | M. Kavitha |
| collection | DOAJ |
| description |
The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.
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| first_indexed | 2024-04-10T17:06:31Z |
| format | Article |
| id | doaj.art-b12f01cb00a54b9e9cedaf9bb1351ac7 |
| institution | Directory Open Access Journal |
| issn | 2241-4487 1792-8036 |
| language | English |
| last_indexed | 2024-04-10T17:06:31Z |
| publishDate | 2023-02-01 |
| publisher | D. G. Pylarinos |
| record_format | Article |
| series | Engineering, Technology & Applied Science Research |
| spelling | doaj.art-b12f01cb00a54b9e9cedaf9bb1351ac72023-02-06T05:00:27ZengD. G. PylarinosEngineering, Technology & Applied Science Research2241-44871792-80362023-02-0113110.48084/etasr.5567Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal AcquisitionM. Kavitha0S. Akhila1Anand Kannan2Department of Electronics and Communication Engineering, JSS Academy of Technical Education, IndiaDepartment of Electronics and Communication Engineering, B.M.S College of Engineering, IndiaTexas Instruments India Private Ltd, India The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB. https://etasr.com/index.php/ETASR/article/view/5567sigma delta modulatorcontinuous-timequantizerDAC |
| spellingShingle | M. Kavitha S. Akhila Anand Kannan Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition Engineering, Technology & Applied Science Research sigma delta modulator continuous-time quantizer DAC |
| title | Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition |
| title_full | Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition |
| title_fullStr | Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition |
| title_full_unstemmed | Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition |
| title_short | Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition |
| title_sort | design and implementation of a second order continuous time σδ modulator for ecg signal acquisition |
| topic | sigma delta modulator continuous-time quantizer DAC |
| url | https://etasr.com/index.php/ETASR/article/view/5567 |
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