Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions

Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions

This paper describes the design of a nonvolatile CPU based on RISC-V that is an open-source and highly flexible instruction set architecture. This CPU incorporates nonvolatile registers utilizing magnetic tunnel junction (MTJ) device, as well as custom instructions specific to the control of these n...

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Bibliographic Details
Main Authors: Masanori Natsui, Keisuke Sakamoto, Takahiro Hanyu
Format: Article
Language:English
Published: Elsevier 2023-07-01
Series:Memories - Materials, Devices, Circuits and Systems
Subjects:
Power gating
Internet of things
CMOS/MTJ-hybrid process
Nonvolatile CPU
Cell-level in-memory computing
Online Access:http://www.sciencedirect.com/science/article/pii/S2773064623000129

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http://www.sciencedirect.com/science/article/pii/S2773064623000129

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