Active realization of fractional order Butterworth lowpass filter using DVCC
This paper presents an active realization of fraction order Butterworth lowpass filter using a differential voltage current conveyor (DVCC) and two fractance devices (FDs). Initially, the DVCC based fractional order system transfer function is developed. Then, the transfer function of the developed...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2020-02-01
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| Series: | Journal of King Saud University: Engineering Sciences |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S1018363918301776 |
| _version_ | 1818990424110399488 |
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| author | Shalabh Kumar Mishra Maneesha Gupta Dharmendra Kumar Upadhyay |
| author_facet | Shalabh Kumar Mishra Maneesha Gupta Dharmendra Kumar Upadhyay |
| author_sort | Shalabh Kumar Mishra |
| collection | DOAJ |
| description | This paper presents an active realization of fraction order Butterworth lowpass filter using a differential voltage current conveyor (DVCC) and two fractance devices (FDs). Initially, the DVCC based fractional order system transfer function is developed. Then, the transfer function of the developed system is equated with the standard fractional order Butterworth equation. By equating this, the generalized condition is obtained for which the developed system behaves like a fractional order Butterworth filter. Further, the effect of current and voltage tracking errors of DVCC, on the system response is investigated using Monte Carlo analysis. Stability of the proposed fractional order Butterworth filter is investigated by pole-zero analysis in complex W-plane. Moreover, the dependency of filter cutoff frequency, on various circuit parameters are investigated using 3D plots. Finally to validate the theoretical results, proposed fractional order Butterworth filter is simulated using R-C ladder network based fractional order capacitor, in PSpice environment using 0.5 μm MIETEC CMOS technology. Keywords: Fractance device, Fractional order filter, Ladder network, W-Plane |
| first_indexed | 2024-12-20T19:54:09Z |
| format | Article |
| id | doaj.art-b27318f1f60b46a4b16d6d44b827eb93 |
| institution | Directory Open Access Journal |
| issn | 1018-3639 |
| language | English |
| last_indexed | 2024-12-20T19:54:09Z |
| publishDate | 2020-02-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Journal of King Saud University: Engineering Sciences |
| spelling | doaj.art-b27318f1f60b46a4b16d6d44b827eb932022-12-21T19:28:12ZengElsevierJournal of King Saud University: Engineering Sciences1018-36392020-02-01322158165Active realization of fractional order Butterworth lowpass filter using DVCCShalabh Kumar Mishra0Maneesha Gupta1Dharmendra Kumar Upadhyay2Division of ECE, Netaji Subhas Institute of Technology, Sector-3, Dwarka, Delhi 110078, IndiaCorresponding author.; Division of ECE, Netaji Subhas Institute of Technology, Sector-3, Dwarka, Delhi 110078, IndiaDivision of ECE, Netaji Subhas Institute of Technology, Sector-3, Dwarka, Delhi 110078, IndiaThis paper presents an active realization of fraction order Butterworth lowpass filter using a differential voltage current conveyor (DVCC) and two fractance devices (FDs). Initially, the DVCC based fractional order system transfer function is developed. Then, the transfer function of the developed system is equated with the standard fractional order Butterworth equation. By equating this, the generalized condition is obtained for which the developed system behaves like a fractional order Butterworth filter. Further, the effect of current and voltage tracking errors of DVCC, on the system response is investigated using Monte Carlo analysis. Stability of the proposed fractional order Butterworth filter is investigated by pole-zero analysis in complex W-plane. Moreover, the dependency of filter cutoff frequency, on various circuit parameters are investigated using 3D plots. Finally to validate the theoretical results, proposed fractional order Butterworth filter is simulated using R-C ladder network based fractional order capacitor, in PSpice environment using 0.5 μm MIETEC CMOS technology. Keywords: Fractance device, Fractional order filter, Ladder network, W-Planehttp://www.sciencedirect.com/science/article/pii/S1018363918301776 |
| spellingShingle | Shalabh Kumar Mishra Maneesha Gupta Dharmendra Kumar Upadhyay Active realization of fractional order Butterworth lowpass filter using DVCC Journal of King Saud University: Engineering Sciences |
| title | Active realization of fractional order Butterworth lowpass filter using DVCC |
| title_full | Active realization of fractional order Butterworth lowpass filter using DVCC |
| title_fullStr | Active realization of fractional order Butterworth lowpass filter using DVCC |
| title_full_unstemmed | Active realization of fractional order Butterworth lowpass filter using DVCC |
| title_short | Active realization of fractional order Butterworth lowpass filter using DVCC |
| title_sort | active realization of fractional order butterworth lowpass filter using dvcc |
| url | http://www.sciencedirect.com/science/article/pii/S1018363918301776 |
| work_keys_str_mv | AT shalabhkumarmishra activerealizationoffractionalorderbutterworthlowpassfilterusingdvcc AT maneeshagupta activerealizationoffractionalorderbutterworthlowpassfilterusingdvcc AT dharmendrakumarupadhyay activerealizationoffractionalorderbutterworthlowpassfilterusingdvcc |