Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA
This research article proposed the reconfigurable Single Instruction Multi Data (SIMD) processor design to speed up the accelerated computing task in IoT operations. Single Instruction Multi Data models leverage the parallel real source to speed up computing accelerated tasks. It proposes the utiliz...
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| Format: | Article |
| Language: | English |
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Faculty of Mechanical Engineering in Slavonski Brod, Faculty of Electrical Engineering in Osijek, Faculty of Civil Engineering in Osijek
2023-01-01
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| Series: | Tehnički Vjesnik |
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| Online Access: | https://hrcak.srce.hr/file/446418 |
| _version_ | 1797206337322483712 |
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| author | Subathradevi Saminathan Ramadevi Ponniah Kavitha Muthurathinam Karthikeyan Somasundaram |
| author_facet | Subathradevi Saminathan Ramadevi Ponniah Kavitha Muthurathinam Karthikeyan Somasundaram |
| author_sort | Subathradevi Saminathan |
| collection | DOAJ |
| description | This research article proposed the reconfigurable Single Instruction Multi Data (SIMD) processor design to speed up the accelerated computing task in IoT operations. Single Instruction Multi Data models leverage the parallel real source to speed up computing accelerated tasks. It proposes the utilization of reconfigurable Kogge Stone-dependent hybrid adder structures, now referred to as KS-CPA, in which reconfiguration occurs during the addition operation. The Least Significant Bits (LSB) are processed using a carry propagate adder, while the Most Significant Bits (MSB) are computed using the Kogge Stone adder. Depending on the data width and device-accessible energy resources, the hybrid configuration of the adder offers the 4-bit, 8-bit, and 16-bit addition. The adder form is identified by a shift in the configuration of its Carry Look-ahead and then by a Kogge Stone Adder (KSA). Throughout the activity, the KS-CLA crossbreed configuration is used to attain the fastest speed and low energy usage. The effectiveness, including its proposed hybrid adder, is evaluated by looking at the speed, energy, and area parameters, including a suitable area use during rapid applications in which both less delay and low power adders are required. Considering these, we are structuring an IoT processor that can be reconfigured to gain from SIMD. We have demonstrated that our hybrid adder-enhanced processor saves energy up to 13% and reduces 27% latency. The proposed 16 and 32-bit adders will boost time, power, and Area Delay Product (ADP) by almost 18-24% and 13-19% respectively. |
| first_indexed | 2024-04-24T09:05:25Z |
| format | Article |
| id | doaj.art-b298c0b400dc49c19d8d03a6e1a521d2 |
| institution | Directory Open Access Journal |
| issn | 1330-3651 1848-6339 |
| language | English |
| last_indexed | 2024-04-24T09:05:25Z |
| publishDate | 2023-01-01 |
| publisher | Faculty of Mechanical Engineering in Slavonski Brod, Faculty of Electrical Engineering in Osijek, Faculty of Civil Engineering in Osijek |
| record_format | Article |
| series | Tehnički Vjesnik |
| spelling | doaj.art-b298c0b400dc49c19d8d03a6e1a521d22024-04-15T19:01:26ZengFaculty of Mechanical Engineering in Slavonski Brod, Faculty of Electrical Engineering in Osijek, Faculty of Civil Engineering in OsijekTehnički Vjesnik1330-36511848-63392023-01-013061975198110.17559/TV-20230404000502Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGASubathradevi Saminathan0Ramadevi Ponniah1Kavitha Muthurathinam2Karthikeyan Somasundaram3Department of Electronics and Communication Engineering, BIT Campus, Anna University, TiruchirappalliDepartment of Electronics and Communication Engineering, BIT Campus, Anna University, TiruchirappalliDepartment of Computer Science and Engineering, K. Ramakrishnan College of Engineering, TiruchirappalliDepartment of Electronics and Communication Engineering, SSM Institute of Engineering and Technology, Dindigul, Tamil Nadu, India-624002This research article proposed the reconfigurable Single Instruction Multi Data (SIMD) processor design to speed up the accelerated computing task in IoT operations. Single Instruction Multi Data models leverage the parallel real source to speed up computing accelerated tasks. It proposes the utilization of reconfigurable Kogge Stone-dependent hybrid adder structures, now referred to as KS-CPA, in which reconfiguration occurs during the addition operation. The Least Significant Bits (LSB) are processed using a carry propagate adder, while the Most Significant Bits (MSB) are computed using the Kogge Stone adder. Depending on the data width and device-accessible energy resources, the hybrid configuration of the adder offers the 4-bit, 8-bit, and 16-bit addition. The adder form is identified by a shift in the configuration of its Carry Look-ahead and then by a Kogge Stone Adder (KSA). Throughout the activity, the KS-CLA crossbreed configuration is used to attain the fastest speed and low energy usage. The effectiveness, including its proposed hybrid adder, is evaluated by looking at the speed, energy, and area parameters, including a suitable area use during rapid applications in which both less delay and low power adders are required. Considering these, we are structuring an IoT processor that can be reconfigured to gain from SIMD. We have demonstrated that our hybrid adder-enhanced processor saves energy up to 13% and reduces 27% latency. The proposed 16 and 32-bit adders will boost time, power, and Area Delay Product (ADP) by almost 18-24% and 13-19% respectively.https://hrcak.srce.hr/file/446418computational capabilitieshybrid adderIoTlow powerreconfigurableSIMD |
| spellingShingle | Subathradevi Saminathan Ramadevi Ponniah Kavitha Muthurathinam Karthikeyan Somasundaram Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA Tehnički Vjesnik computational capabilities hybrid adder IoT low power reconfigurable SIMD |
| title | Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA |
| title_full | Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA |
| title_fullStr | Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA |
| title_full_unstemmed | Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA |
| title_short | Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA |
| title_sort | internet of things based reconfigurable simd processor for high speed end devices in fpga |
| topic | computational capabilities hybrid adder IoT low power reconfigurable SIMD |
| url | https://hrcak.srce.hr/file/446418 |
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