New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. Howev...

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Main Authors: Giulia Santoro, Giovanna Turvani, Mariagrazia Graziano
Format: Article
Language:English
Published: MDPI AG 2019-05-01
Series:Micromachines
Subjects:
Online Access:https://www.mdpi.com/2072-666X/10/6/368
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author Giulia Santoro
Giovanna Turvani
Mariagrazia Graziano
author_facet Giulia Santoro
Giovanna Turvani
Mariagrazia Graziano
author_sort Giulia Santoro
collection DOAJ
description Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal−oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.
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spelling doaj.art-b373f02968b84a76b70ab90c71f92a3c2022-12-21T19:26:57ZengMDPI AGMicromachines2072-666X2019-05-0110636810.3390/mi10060368mi10060368New Logic-In-Memory Paradigms: An Architectural and Technological PerspectiveGiulia Santoro0Giovanna Turvani1Mariagrazia Graziano2Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino; Corso Castelfidardo 39, 10129 Torino, ItalyDipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino; Corso Castelfidardo 39, 10129 Torino, ItalyDipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino; Corso Castelfidardo 39, 10129 Torino, ItalyProcessing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal−oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.https://www.mdpi.com/2072-666X/10/6/368in-memory computinglogic-in-memorynon-von Neumann architectureconfigurable logic-in-memory architecturememory wallconvolutional neural networksemerging technologiesperpendicular Nano Magnetic Logic (pNML)
spellingShingle Giulia Santoro
Giovanna Turvani
Mariagrazia Graziano
New Logic-In-Memory Paradigms: An Architectural and Technological Perspective
Micromachines
in-memory computing
logic-in-memory
non-von Neumann architecture
configurable logic-in-memory architecture
memory wall
convolutional neural networks
emerging technologies
perpendicular Nano Magnetic Logic (pNML)
title New Logic-In-Memory Paradigms: An Architectural and Technological Perspective
title_full New Logic-In-Memory Paradigms: An Architectural and Technological Perspective
title_fullStr New Logic-In-Memory Paradigms: An Architectural and Technological Perspective
title_full_unstemmed New Logic-In-Memory Paradigms: An Architectural and Technological Perspective
title_short New Logic-In-Memory Paradigms: An Architectural and Technological Perspective
title_sort new logic in memory paradigms an architectural and technological perspective
topic in-memory computing
logic-in-memory
non-von Neumann architecture
configurable logic-in-memory architecture
memory wall
convolutional neural networks
emerging technologies
perpendicular Nano Magnetic Logic (pNML)
url https://www.mdpi.com/2072-666X/10/6/368
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