Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects
High-performance sparse matrix multipliers are essential for deep learning applications, and as big data analytics continues to evolve, specialized accelerators are also needed to efficiently handle sparse matrix operations. This paper proposes a modified, configurable, outer product based architect...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Elsevier
2024-03-01
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| Series: | Alexandria Engineering Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S1110016824001145 |
| _version_ | 1797319504499310592 |
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| author | G. Noble S. Nalesh S. Kala Akash Kumar |
| author_facet | G. Noble S. Nalesh S. Kala Akash Kumar |
| author_sort | G. Noble |
| collection | DOAJ |
| description | High-performance sparse matrix multipliers are essential for deep learning applications, and as big data analytics continues to evolve, specialized accelerators are also needed to efficiently handle sparse matrix operations. This paper proposes a modified, configurable, outer product based architecture for sparse matrix multiplication, and explores design space of the proposed architecture. The performance of various architecture configurations has been examined for input samples with similar characteristics. The proposed architecture has been implemented on Xilinx Kintex-7 FPGA using 32-bit single precision floating-point arithmetic and also in 8-bit, 16-bit and 32-bit fixed-point arithmetic formats. The effect of quantization in the proposed architecture has been analyzed extensively and the results have been reported. The performance of the proposed architecture has been compared with state-of-the-art implementations, and an improvement of 9.21% has been observed in the performance. |
| first_indexed | 2024-03-08T04:07:51Z |
| format | Article |
| id | doaj.art-b3998b2c00ed448089686c3f1aa0b3fa |
| institution | Directory Open Access Journal |
| issn | 1110-0168 |
| language | English |
| last_indexed | 2024-03-08T04:07:51Z |
| publishDate | 2024-03-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Alexandria Engineering Journal |
| spelling | doaj.art-b3998b2c00ed448089686c3f1aa0b3fa2024-02-09T04:47:45ZengElsevierAlexandria Engineering Journal1110-01682024-03-01918494Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effectsG. Noble0S. Nalesh1S. Kala2Akash Kumar3Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Kottayam, 686635, Kerala, IndiaDepartment of Electronics, Cochin University of Science And Technology, Kochi, 682022, Kerala, IndiaDepartment of Electronics and Communication Engineering, Indian Institute of Information Technology, Kottayam, 686635, Kerala, India; Corresponding author.Center for Advancing Electronics Dresden-CFAED, Technische Universität Dresden, Dresden, 01062, GermanyHigh-performance sparse matrix multipliers are essential for deep learning applications, and as big data analytics continues to evolve, specialized accelerators are also needed to efficiently handle sparse matrix operations. This paper proposes a modified, configurable, outer product based architecture for sparse matrix multiplication, and explores design space of the proposed architecture. The performance of various architecture configurations has been examined for input samples with similar characteristics. The proposed architecture has been implemented on Xilinx Kintex-7 FPGA using 32-bit single precision floating-point arithmetic and also in 8-bit, 16-bit and 32-bit fixed-point arithmetic formats. The effect of quantization in the proposed architecture has been analyzed extensively and the results have been reported. The performance of the proposed architecture has been compared with state-of-the-art implementations, and an improvement of 9.21% has been observed in the performance.http://www.sciencedirect.com/science/article/pii/S1110016824001145AcceleratorFPGAOuter productSparse matrix multiplicationSpGEMMQuantization |
| spellingShingle | G. Noble S. Nalesh S. Kala Akash Kumar Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects Alexandria Engineering Journal Accelerator FPGA Outer product Sparse matrix multiplication SpGEMM Quantization |
| title | Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects |
| title_full | Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects |
| title_fullStr | Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects |
| title_full_unstemmed | Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects |
| title_short | Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects |
| title_sort | configurable sparse matrix matrix multiplication accelerator on fpga a systematic design space exploration approach with quantization effects |
| topic | Accelerator FPGA Outer product Sparse matrix multiplication SpGEMM Quantization |
| url | http://www.sciencedirect.com/science/article/pii/S1110016824001145 |
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