Efficient Implementation of a Symbol Timing Estimator for Broadband PLC
Broadband Power Line Communications (PLC) have taken advantage of the research advances in multi-carrier modulations to mitigate frequency selective fading, and their adoption opens up a myriad of applications in the field of sensory and automation systems, multimedia connectivity or smart spaces. N...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2015-08-01
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| Series: | Sensors |
| Subjects: | |
| Online Access: | http://www.mdpi.com/1424-8220/15/8/20825 |
| _version_ | 1811186368934576128 |
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| author | Francisco Nombela Enrique García Raúl Mateos Álvaro Hernández |
| author_facet | Francisco Nombela Enrique García Raúl Mateos Álvaro Hernández |
| author_sort | Francisco Nombela |
| collection | DOAJ |
| description | Broadband Power Line Communications (PLC) have taken advantage of the research advances in multi-carrier modulations to mitigate frequency selective fading, and their adoption opens up a myriad of applications in the field of sensory and automation systems, multimedia connectivity or smart spaces. Nonetheless, the use of these multi-carrier modulations, such as Wavelet-OFDM, requires a highly accurate symbol timing estimation for reliably recovering of transmitted data. Furthermore, the PLC channel presents some particularities that prevent the direct use of previous synchronization algorithms proposed in wireless communication systems. Therefore more research effort should be involved in the design and implementation of novel and robust synchronization algorithms for PLC, thus enabling real-time synchronization. This paper proposes a symbol timing estimator for broadband PLC based on cross-correlation with multilevel complementary sequences or Zadoff-Chu sequences and its efficient implementation in a FPGA; the obtained results show a 90% of success rate in symbol timing estimation for a certain PLC channel model and a reduced resource consumption for its implementation in a Xilinx Kyntex FPGA. |
| first_indexed | 2024-04-11T13:44:57Z |
| format | Article |
| id | doaj.art-b3dc44710ac5452fa2ef985391c2d73b |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-04-11T13:44:57Z |
| publishDate | 2015-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-b3dc44710ac5452fa2ef985391c2d73b2022-12-22T04:21:07ZengMDPI AGSensors1424-82202015-08-01158208252084410.3390/s150820825s150820825Efficient Implementation of a Symbol Timing Estimator for Broadband PLCFrancisco Nombela0Enrique García1Raúl Mateos2Álvaro Hernández3Electronics Department, University of Alcalá, Campus Universitario s/n, Alcalá de Henares, Madrid 28805, SpainElectronics Department, University of Alcalá, Campus Universitario s/n, Alcalá de Henares, Madrid 28805, SpainElectronics Department, University of Alcalá, Campus Universitario s/n, Alcalá de Henares, Madrid 28805, SpainElectronics Department, University of Alcalá, Campus Universitario s/n, Alcalá de Henares, Madrid 28805, SpainBroadband Power Line Communications (PLC) have taken advantage of the research advances in multi-carrier modulations to mitigate frequency selective fading, and their adoption opens up a myriad of applications in the field of sensory and automation systems, multimedia connectivity or smart spaces. Nonetheless, the use of these multi-carrier modulations, such as Wavelet-OFDM, requires a highly accurate symbol timing estimation for reliably recovering of transmitted data. Furthermore, the PLC channel presents some particularities that prevent the direct use of previous synchronization algorithms proposed in wireless communication systems. Therefore more research effort should be involved in the design and implementation of novel and robust synchronization algorithms for PLC, thus enabling real-time synchronization. This paper proposes a symbol timing estimator for broadband PLC based on cross-correlation with multilevel complementary sequences or Zadoff-Chu sequences and its efficient implementation in a FPGA; the obtained results show a 90% of success rate in symbol timing estimation for a certain PLC channel model and a reduced resource consumption for its implementation in a Xilinx Kyntex FPGA.http://www.mdpi.com/1424-8220/15/8/20825Power-Line Communicationssymbol timing estimationcomplementary sequencesZadoff-Chu sequencesFPGA-based architecture |
| spellingShingle | Francisco Nombela Enrique García Raúl Mateos Álvaro Hernández Efficient Implementation of a Symbol Timing Estimator for Broadband PLC Sensors Power-Line Communications symbol timing estimation complementary sequences Zadoff-Chu sequences FPGA-based architecture |
| title | Efficient Implementation of a Symbol Timing Estimator for Broadband PLC |
| title_full | Efficient Implementation of a Symbol Timing Estimator for Broadband PLC |
| title_fullStr | Efficient Implementation of a Symbol Timing Estimator for Broadband PLC |
| title_full_unstemmed | Efficient Implementation of a Symbol Timing Estimator for Broadband PLC |
| title_short | Efficient Implementation of a Symbol Timing Estimator for Broadband PLC |
| title_sort | efficient implementation of a symbol timing estimator for broadband plc |
| topic | Power-Line Communications symbol timing estimation complementary sequences Zadoff-Chu sequences FPGA-based architecture |
| url | http://www.mdpi.com/1424-8220/15/8/20825 |
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