An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation
In-memory computing (IMC) has been widely accepted to be an effective method to improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored in columns, which contradicts SRAM write patterns and requires additional data movement. In this paper, an 8T SRAM arra...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-01-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/3/300 |
| _version_ | 1797406925965492224 |
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| author | Jin Zhang Zhiting Lin Xiulong Wu Chunyu Peng Wenjuan Lu Qiang Zhao Junning Chen |
| author_facet | Jin Zhang Zhiting Lin Xiulong Wu Chunyu Peng Wenjuan Lu Qiang Zhao Junning Chen |
| author_sort | Jin Zhang |
| collection | DOAJ |
| description | In-memory computing (IMC) has been widely accepted to be an effective method to improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored in columns, which contradicts SRAM write patterns and requires additional data movement. In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes. In the ternary multiplication mode, the reference voltage generation column is not required. The energy of computing is only 1.273 fJ/bit. In the unsigned multibit multiplication mode, discharge and charging paths are used to enlarge the voltage difference of the least significant bit. In the logic operation mode, different types of operations (e.g., IMP, OR, NOR, XNOR, and XOR) are achieved in a single cycle. The frequency of logic computing is up to 909 MHz. |
| first_indexed | 2024-03-09T03:33:49Z |
| format | Article |
| id | doaj.art-b58339308c10400a89fd2a1ae4beb97c |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T03:33:49Z |
| publishDate | 2021-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-b58339308c10400a89fd2a1ae4beb97c2023-12-03T14:51:11ZengMDPI AGElectronics2079-92922021-01-0110330010.3390/electronics10030300An 8T SRAM Array with Configurable Word Lines for In-Memory Computing OperationJin Zhang0Zhiting Lin1Xiulong Wu2Chunyu Peng3Wenjuan Lu4Qiang Zhao5Junning Chen6School of Electronics and Information Engineering, Anhui University, Hefei 230601, ChinaSchool of Electronics and Information Engineering, Anhui University, Hefei 230601, ChinaSchool of Electronics and Information Engineering, Anhui University, Hefei 230601, ChinaSchool of Electronics and Information Engineering, Anhui University, Hefei 230601, ChinaSchool of Electronics and Information Engineering, Anhui University, Hefei 230601, ChinaSchool of Electronics and Information Engineering, Anhui University, Hefei 230601, ChinaSchool of Electronics and Information Engineering, Anhui University, Hefei 230601, ChinaIn-memory computing (IMC) has been widely accepted to be an effective method to improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored in columns, which contradicts SRAM write patterns and requires additional data movement. In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes. In the ternary multiplication mode, the reference voltage generation column is not required. The energy of computing is only 1.273 fJ/bit. In the unsigned multibit multiplication mode, discharge and charging paths are used to enlarge the voltage difference of the least significant bit. In the logic operation mode, different types of operations (e.g., IMP, OR, NOR, XNOR, and XOR) are achieved in a single cycle. The frequency of logic computing is up to 909 MHz.https://www.mdpi.com/2079-9292/10/3/300ternary multiplicationunsigned multibit multiplicationlogic operationin-memory computing (IMC)unidirectional charging and discharging |
| spellingShingle | Jin Zhang Zhiting Lin Xiulong Wu Chunyu Peng Wenjuan Lu Qiang Zhao Junning Chen An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation Electronics ternary multiplication unsigned multibit multiplication logic operation in-memory computing (IMC) unidirectional charging and discharging |
| title | An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation |
| title_full | An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation |
| title_fullStr | An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation |
| title_full_unstemmed | An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation |
| title_short | An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation |
| title_sort | 8t sram array with configurable word lines for in memory computing operation |
| topic | ternary multiplication unsigned multibit multiplication logic operation in-memory computing (IMC) unidirectional charging and discharging |
| url | https://www.mdpi.com/2079-9292/10/3/300 |
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