Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic
Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and also results in more delay. Therefore, in this paper, a method to reduce the computation delay of hierarchy multiplier by...
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| Format: | Article |
| Language: | English |
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Elsevier
2017-02-01
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| Series: | Engineering Science and Technology, an International Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215098616303202 |
| _version_ | 1818548183826956288 |
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| author | Mohan Shoba Rangaswamy Nakkeeran |
| author_facet | Mohan Shoba Rangaswamy Nakkeeran |
| author_sort | Mohan Shoba |
| collection | DOAJ |
| description | Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and also results in more delay. Therefore, in this paper, a method to reduce the computation delay of hierarchy multiplier by employing CslA and Binary to Excess 1 Converter (BEC) is proposed. The use of BEC eliminates the n/4 number of adders, existing in the conventional addition scheme, where n denotes the multiplier input width. As the area of the hierarchy multiplier is determined by its base multiplier, the base multiplier is realized with the proposed Vedic multiplier, which has small area and operates with less delay than the conventional multipliers. In addition, the reduction of power consumption in the hierarchy multiplier can be ensured by implementing the designed multiplier with full swing Gate Diffusion Input (GDI) logic. The performances of the proposed and the existing multipliers are evaluated by Cadence SPICE simulator using 45 nm technology model. From the simulation results, the performance parameters namely, delay and power consumption are calculated. Further, the area is measured from the corresponding layout for the same technology model. It is examined from the results that the proposed multiplier operates with 17% lesser power delay product than the recently reported hierarchy multiplier. The Monte Carlo simulation is performed to understand the robustness of the proposed hierarchy multiplier. |
| first_indexed | 2024-12-12T08:16:31Z |
| format | Article |
| id | doaj.art-b5ba47f7511440948d3079d9cf29b086 |
| institution | Directory Open Access Journal |
| issn | 2215-0986 |
| language | English |
| last_indexed | 2024-12-12T08:16:31Z |
| publishDate | 2017-02-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Engineering Science and Technology, an International Journal |
| spelling | doaj.art-b5ba47f7511440948d3079d9cf29b0862022-12-22T00:31:33ZengElsevierEngineering Science and Technology, an International Journal2215-09862017-02-0120132133110.1016/j.jestch.2016.06.007Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logicMohan ShobaRangaswamy NakkeeranHierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and also results in more delay. Therefore, in this paper, a method to reduce the computation delay of hierarchy multiplier by employing CslA and Binary to Excess 1 Converter (BEC) is proposed. The use of BEC eliminates the n/4 number of adders, existing in the conventional addition scheme, where n denotes the multiplier input width. As the area of the hierarchy multiplier is determined by its base multiplier, the base multiplier is realized with the proposed Vedic multiplier, which has small area and operates with less delay than the conventional multipliers. In addition, the reduction of power consumption in the hierarchy multiplier can be ensured by implementing the designed multiplier with full swing Gate Diffusion Input (GDI) logic. The performances of the proposed and the existing multipliers are evaluated by Cadence SPICE simulator using 45 nm technology model. From the simulation results, the performance parameters namely, delay and power consumption are calculated. Further, the area is measured from the corresponding layout for the same technology model. It is examined from the results that the proposed multiplier operates with 17% lesser power delay product than the recently reported hierarchy multiplier. The Monte Carlo simulation is performed to understand the robustness of the proposed hierarchy multiplier.http://www.sciencedirect.com/science/article/pii/S2215098616303202MultiplierFS-GDI logicCslABEC converter4-2 compressor |
| spellingShingle | Mohan Shoba Rangaswamy Nakkeeran Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic Engineering Science and Technology, an International Journal Multiplier FS-GDI logic CslA BEC converter 4-2 compressor |
| title | Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic |
| title_full | Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic |
| title_fullStr | Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic |
| title_full_unstemmed | Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic |
| title_short | Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic |
| title_sort | energy and area efficient hierarchy multiplier architecture based on vedic mathematics and gdi logic |
| topic | Multiplier FS-GDI logic CslA BEC converter 4-2 compressor |
| url | http://www.sciencedirect.com/science/article/pii/S2215098616303202 |
| work_keys_str_mv | AT mohanshoba energyandareaefficienthierarchymultiplierarchitecturebasedonvedicmathematicsandgdilogic AT rangaswamynakkeeran energyandareaefficienthierarchymultiplierarchitecturebasedonvedicmathematicsandgdilogic |