Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic
Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and also results in more delay. Therefore, in this paper, a method to reduce the computation delay of hierarchy multiplier by...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2017-02-01
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| Series: | Engineering Science and Technology, an International Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215098616303202 |