Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformit...

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Main Authors: Miron Kłosowski, Yichuang Sun
Format: Article
Language:English
Published: MDPI AG 2020-10-01
Series:Sensors
Subjects:
Online Access:https://www.mdpi.com/1424-8220/20/20/5921
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author Miron Kłosowski
Yichuang Sun
author_facet Miron Kłosowski
Yichuang Sun
author_sort Miron Kłosowski
collection DOAJ
description In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.
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spelling doaj.art-b74b3831d2514ecba03e40cc3f040ddd2023-11-20T17:52:11ZengMDPI AGSensors1424-82202020-10-012020592110.3390/s20205921Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image SensorsMiron Kłosowski0Yichuang Sun1Faculty of Electronics, Telecommunications and Informatics, Gdańsk University of Technology, 11/12 Gabriela Narutowicza Street, 80-233 Gdańsk, PolandSchool of Engineering and Computer Science, University of Hertfordshire, Hatfield, Herts AL10 9AB, UKIn the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.https://www.mdpi.com/1424-8220/20/20/5921image sensorfixed pattern noisegain correctionoffset correctionintegral nonlinearity correctiontime-mode ADC
spellingShingle Miron Kłosowski
Yichuang Sun
Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
Sensors
image sensor
fixed pattern noise
gain correction
offset correction
integral nonlinearity correction
time-mode ADC
title Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
title_full Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
title_fullStr Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
title_full_unstemmed Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
title_short Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
title_sort fixed pattern noise reduction and linearity improvement in time mode cmos image sensors
topic image sensor
fixed pattern noise
gain correction
offset correction
integral nonlinearity correction
time-mode ADC
url https://www.mdpi.com/1424-8220/20/20/5921
work_keys_str_mv AT mironkłosowski fixedpatternnoisereductionandlinearityimprovementintimemodecmosimagesensors
AT yichuangsun fixedpatternnoisereductionandlinearityimprovementintimemodecmosimagesensors