Low Power Neural Network by Reducing SRAM Operating Voltage
With advancements in machine learning technology, networks are becoming increasingly complex, and the extent of the computation involved is increasing. Consequently, the computation time and power consumption of the learning process are increased. The error tolerance of neural networks has attracted...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2022-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9936634/ |
| _version_ | 1817975601959534592 |
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| author | Keisuke Kozu Yuya Tanabe Masato Kitakami Kazuteru Namba |
| author_facet | Keisuke Kozu Yuya Tanabe Masato Kitakami Kazuteru Namba |
| author_sort | Keisuke Kozu |
| collection | DOAJ |
| description | With advancements in machine learning technology, networks are becoming increasingly complex, and the extent of the computation involved is increasing. Consequently, the computation time and power consumption of the learning process are increased. The error tolerance of neural networks has attracted attention as an approach to solving this problem. Because neural networks can tolerate small errors, it is possible to reduce the calculation speed and power consumption at the expense of accuracy. In this study, we propose a method to reduce the power consumption of the circuit by lowering the operating voltage of the static random-access memory (SRAM) that is utilized to store the weights. In the proposed method, using two different operating voltages of SRAM, we used different bit error rates (BERs) for error-tolerant and non-error-tolerant. We demonstrated the relationship between the BER and recognition rate, and the appropriate combination of the BER and circuit configuration that maintains a high recognition rate. |
| first_indexed | 2024-04-13T21:52:04Z |
| format | Article |
| id | doaj.art-b7fac73a34ee4d1bb30eb8ec40a2e4f3 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-13T21:52:04Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-b7fac73a34ee4d1bb30eb8ec40a2e4f32022-12-22T02:28:24ZengIEEEIEEE Access2169-35362022-01-011011698211698610.1109/ACCESS.2022.32192089936634Low Power Neural Network by Reducing SRAM Operating VoltageKeisuke Kozu0Yuya Tanabe1Masato Kitakami2Kazuteru Namba3https://orcid.org/0000-0002-8316-7281Graduate School of Science and Engineering, Chiba University, Chiba, JapanGraduate School of Science and Engineering, Chiba University, Chiba, JapanGraduate School of Engineering, Chiba University, Chiba, JapanGraduate School of Engineering, Chiba University, Chiba, JapanWith advancements in machine learning technology, networks are becoming increasingly complex, and the extent of the computation involved is increasing. Consequently, the computation time and power consumption of the learning process are increased. The error tolerance of neural networks has attracted attention as an approach to solving this problem. Because neural networks can tolerate small errors, it is possible to reduce the calculation speed and power consumption at the expense of accuracy. In this study, we propose a method to reduce the power consumption of the circuit by lowering the operating voltage of the static random-access memory (SRAM) that is utilized to store the weights. In the proposed method, using two different operating voltages of SRAM, we used different bit error rates (BERs) for error-tolerant and non-error-tolerant. We demonstrated the relationship between the BER and recognition rate, and the appropriate combination of the BER and circuit configuration that maintains a high recognition rate.https://ieeexplore.ieee.org/document/9936634/Neural networkSRAMapproximate computing |
| spellingShingle | Keisuke Kozu Yuya Tanabe Masato Kitakami Kazuteru Namba Low Power Neural Network by Reducing SRAM Operating Voltage IEEE Access Neural network SRAM approximate computing |
| title | Low Power Neural Network by Reducing SRAM Operating Voltage |
| title_full | Low Power Neural Network by Reducing SRAM Operating Voltage |
| title_fullStr | Low Power Neural Network by Reducing SRAM Operating Voltage |
| title_full_unstemmed | Low Power Neural Network by Reducing SRAM Operating Voltage |
| title_short | Low Power Neural Network by Reducing SRAM Operating Voltage |
| title_sort | low power neural network by reducing sram operating voltage |
| topic | Neural network SRAM approximate computing |
| url | https://ieeexplore.ieee.org/document/9936634/ |
| work_keys_str_mv | AT keisukekozu lowpowerneuralnetworkbyreducingsramoperatingvoltage AT yuyatanabe lowpowerneuralnetworkbyreducingsramoperatingvoltage AT masatokitakami lowpowerneuralnetworkbyreducingsramoperatingvoltage AT kazuterunamba lowpowerneuralnetworkbyreducingsramoperatingvoltage |