A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography
This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>...
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MDPI AG
2021-11-01
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| Online Access: | https://www.mdpi.com/2079-9292/10/21/2698 |
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| author | Muhammad Rashid Mohammad Mazyad Hazzazi Sikandar Zulqarnain Khan Adel R. Alharbi Asher Sajid Amer Aljaedi |
| author_facet | Muhammad Rashid Mohammad Mazyad Hazzazi Sikandar Zulqarnain Khan Adel R. Alharbi Asher Sajid Amer Aljaedi |
| author_sort | Muhammad Rashid |
| collection | DOAJ |
| description | This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula> with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula> is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W) and Kintex-7 (61 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency. |
| first_indexed | 2024-03-10T06:04:55Z |
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| issn | 2079-9292 |
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| last_indexed | 2024-03-10T06:04:55Z |
| publishDate | 2021-11-01 |
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| series | Electronics |
| spelling | doaj.art-b97e7b65edd54319b13a8d39866ac9022023-11-22T20:39:31ZengMDPI AGElectronics2079-92922021-11-011021269810.3390/electronics10212698A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve CryptographyMuhammad Rashid0Mohammad Mazyad Hazzazi1Sikandar Zulqarnain Khan2Adel R. Alharbi3Asher Sajid4Amer Aljaedi5Department of Computer Engineering, Umm Al-Qura University, Makkah 21955, Saudi ArabiaDepartment of Mathematics, College of Science, King Khalid University, Abha 61413, Saudi ArabiaDepartment of Aeronautical Engineering, Estonian Aviation Academy, 61707 Tartu, EstoniaCollege of Computing and Information Technology, University of Tabuk, Tabuk 71491, Saudi ArabiaDepartment of Electrical Engineering, Bahria University, Islamabad 44000, PakistanCollege of Computing and Information Technology, University of Tabuk, Tabuk 71491, Saudi ArabiaThis paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula> with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula> is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W) and Kintex-7 (61 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.https://www.mdpi.com/2079-9292/10/21/2698elliptic-curve cryptographypoint multiplicationhardware architectureFPGA |
| spellingShingle | Muhammad Rashid Mohammad Mazyad Hazzazi Sikandar Zulqarnain Khan Adel R. Alharbi Asher Sajid Amer Aljaedi A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography Electronics elliptic-curve cryptography point multiplication hardware architecture FPGA |
| title | A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography |
| title_full | A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography |
| title_fullStr | A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography |
| title_full_unstemmed | A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography |
| title_short | A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography |
| title_sort | novel low area point multiplication architecture for elliptic curve cryptography |
| topic | elliptic-curve cryptography point multiplication hardware architecture FPGA |
| url | https://www.mdpi.com/2079-9292/10/21/2698 |
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