A Methodology to Design Static NCL Libraries
The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for unive...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-06-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | https://www.mdpi.com/2079-9268/12/2/31 |
| _version_ | 1797485780344504320 |
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| author | Toi Le Thanh Lac Truong Tri Trang Hoang |
| author_facet | Toi Le Thanh Lac Truong Tri Trang Hoang |
| author_sort | Toi Le Thanh |
| collection | DOAJ |
| description | The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption. |
| first_indexed | 2024-03-09T23:24:44Z |
| format | Article |
| id | doaj.art-bc03f0affc9145c5a50990b5d2950399 |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-03-09T23:24:44Z |
| publishDate | 2022-06-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-bc03f0affc9145c5a50990b5d29503992023-11-23T17:21:14ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682022-06-011223110.3390/jlpea12020031A Methodology to Design Static NCL LibrariesToi Le Thanh0Lac Truong Tri1Trang Hoang2Department of Electronics Engineering, Faculty of Electricals and Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), 268 Ly Thuong Kiet Street, District 10, Ho Chi Minh City 700000, VietnamDepartment of Electronics Engineering, Faculty of Electricals and Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), 268 Ly Thuong Kiet Street, District 10, Ho Chi Minh City 700000, VietnamDepartment of Electronics Engineering, Faculty of Electricals and Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), 268 Ly Thuong Kiet Street, District 10, Ho Chi Minh City 700000, VietnamThe Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.https://www.mdpi.com/2079-9268/12/2/31NCL cell librarythreshold gateasynchronous methodNull Convention Logic |
| spellingShingle | Toi Le Thanh Lac Truong Tri Trang Hoang A Methodology to Design Static NCL Libraries Journal of Low Power Electronics and Applications NCL cell library threshold gate asynchronous method Null Convention Logic |
| title | A Methodology to Design Static NCL Libraries |
| title_full | A Methodology to Design Static NCL Libraries |
| title_fullStr | A Methodology to Design Static NCL Libraries |
| title_full_unstemmed | A Methodology to Design Static NCL Libraries |
| title_short | A Methodology to Design Static NCL Libraries |
| title_sort | methodology to design static ncl libraries |
| topic | NCL cell library threshold gate asynchronous method Null Convention Logic |
| url | https://www.mdpi.com/2079-9268/12/2/31 |
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