HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis
Spin Transfer Torque Random Access Memory (STT-RAM) is an emerging Non-Volatile Memory (NVM) technology that has garnered attention to overcome the drawbacks of conventional CMOS-based technologies. However, such technologies must be evaluated before deployment under real workloads and architecture....
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10414783/ |
| _version_ | 1797323939094986752 |
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| author | Saeed Seyedfaraji Markus Bichl Asad Aftab Semeen Rehman |
| author_facet | Saeed Seyedfaraji Markus Bichl Asad Aftab Semeen Rehman |
| author_sort | Saeed Seyedfaraji |
| collection | DOAJ |
| description | Spin Transfer Torque Random Access Memory (STT-RAM) is an emerging Non-Volatile Memory (NVM) technology that has garnered attention to overcome the drawbacks of conventional CMOS-based technologies. However, such technologies must be evaluated before deployment under real workloads and architecture. But there is a lack of available open-source STT-RAM-based system evaluation framework, which hampers research and experimentation and impacts the adoption of STT-RAM in a system. This paper proposes a novel, extendable STT-RAM memory controller design integrated inside the gem5 simulator. Our framework enables understanding various aspects of STT-RAM, i.e., power, delay, clock cycles, energy, and system throughput. We will open-source our HOPE framework, which will fuel research and aid in accelerating the development of future system architectures based on STT-RAM. It will also facilitate the user for further tool enhancement. |
| first_indexed | 2024-03-08T05:35:16Z |
| format | Article |
| id | doaj.art-bcee21528a994e93be6e63c8fb8597cf |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-08T05:35:16Z |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-bcee21528a994e93be6e63c8fb8597cf2024-02-06T00:01:43ZengIEEEIEEE Access2169-35362024-01-0112165981660910.1109/ACCESS.2024.335889110414783HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform AnalysisSaeed Seyedfaraji0https://orcid.org/0000-0003-0085-6282Markus Bichl1https://orcid.org/0009-0007-7469-3259Asad Aftab2https://orcid.org/0009-0004-6669-5156Semeen Rehman3https://orcid.org/0000-0002-8972-0949Faculty of Electrical Engineering and Information Technology, Vienna University of Technology (TU Wien), Vienna, AustriaFaculty of Electrical Engineering and Information Technology, Vienna University of Technology (TU Wien), Vienna, AustriaFaculty of Electrical Engineering and Information Technology, Vienna University of Technology (TU Wien), Vienna, AustriaFaculty of Electrical Engineering and Information Technology, Vienna University of Technology (TU Wien), Vienna, AustriaSpin Transfer Torque Random Access Memory (STT-RAM) is an emerging Non-Volatile Memory (NVM) technology that has garnered attention to overcome the drawbacks of conventional CMOS-based technologies. However, such technologies must be evaluated before deployment under real workloads and architecture. But there is a lack of available open-source STT-RAM-based system evaluation framework, which hampers research and experimentation and impacts the adoption of STT-RAM in a system. This paper proposes a novel, extendable STT-RAM memory controller design integrated inside the gem5 simulator. Our framework enables understanding various aspects of STT-RAM, i.e., power, delay, clock cycles, energy, and system throughput. We will open-source our HOPE framework, which will fuel research and aid in accelerating the development of future system architectures based on STT-RAM. It will also facilitate the user for further tool enhancement.https://ieeexplore.ieee.org/document/10414783/Non-volatile memorySTT-RAMpower estimationgem5emerging technologies |
| spellingShingle | Saeed Seyedfaraji Markus Bichl Asad Aftab Semeen Rehman HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis IEEE Access Non-volatile memory STT-RAM power estimation gem5 emerging technologies |
| title | HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis |
| title_full | HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis |
| title_fullStr | HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis |
| title_full_unstemmed | HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis |
| title_short | HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis |
| title_sort | hope holistic stt ram architecture exploration framework for future cross platform analysis |
| topic | Non-volatile memory STT-RAM power estimation gem5 emerging technologies |
| url | https://ieeexplore.ieee.org/document/10414783/ |
| work_keys_str_mv | AT saeedseyedfaraji hopeholisticsttramarchitectureexplorationframeworkforfuturecrossplatformanalysis AT markusbichl hopeholisticsttramarchitectureexplorationframeworkforfuturecrossplatformanalysis AT asadaftab hopeholisticsttramarchitectureexplorationframeworkforfuturecrossplatformanalysis AT semeenrehman hopeholisticsttramarchitectureexplorationframeworkforfuturecrossplatformanalysis |