Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to su...
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| Format: | Article |
| Language: | English |
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MDPI AG
2024-02-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/24/5/1416 |
| _version_ | 1797263903323848704 |
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| author | Marc Majoral Javier Arribas Carles Fernández-Prades |
| author_facet | Marc Majoral Javier Arribas Carles Fernández-Prades |
| author_sort | Marc Majoral |
| collection | DOAJ |
| description | This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>C</mi><mo>/</mo><msub><mi>N</mi><mn>0</mn></msub></mrow></semantics></math></inline-formula>) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques. |
| first_indexed | 2024-04-25T00:20:24Z |
| format | Article |
| id | doaj.art-bd403378dc964567938f55ebd0ae635c |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-04-25T00:20:24Z |
| publishDate | 2024-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-bd403378dc964567938f55ebd0ae635c2024-03-12T16:54:40ZengMDPI AGSensors1424-82202024-02-01245141610.3390/s24051416Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array PlatformMarc Majoral0Javier Arribas1Carles Fernández-Prades2Centre Tecnològic de Telecomunicacions de Catalunya (CTTC/CERCA), Parc Mediterrani de la Tecnologia, Building B4, Av. Carl Friedrich Gauss 7, 08860 Castelldefels, SpainCentre Tecnològic de Telecomunicacions de Catalunya (CTTC/CERCA), Parc Mediterrani de la Tecnologia, Building B4, Av. Carl Friedrich Gauss 7, 08860 Castelldefels, SpainCentre Tecnològic de Telecomunicacions de Catalunya (CTTC/CERCA), Parc Mediterrani de la Tecnologia, Building B4, Av. Carl Friedrich Gauss 7, 08860 Castelldefels, SpainThis paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>C</mi><mo>/</mo><msub><mi>N</mi><mn>0</mn></msub></mrow></semantics></math></inline-formula>) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques.https://www.mdpi.com/1424-8220/24/5/1416GNSSFPGAsystem on chipSoC-FPGAhigh-sensitivity GNSS receiversoftware-defined radio |
| spellingShingle | Marc Majoral Javier Arribas Carles Fernández-Prades Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform Sensors GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio |
| title | Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform |
| title_full | Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform |
| title_fullStr | Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform |
| title_full_unstemmed | Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform |
| title_short | Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform |
| title_sort | implementation of a high sensitivity global navigation satellite system receiver on a system on chip field programmable gate array platform |
| topic | GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio |
| url | https://www.mdpi.com/1424-8220/24/5/1416 |
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