Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform
Continued scaling in accordance with Moore’s law is becoming increasingly difficult. Pitch shrinkage and standard cell height reduction via design technology co-optimization with design rules have sustained this scaling until recently. However, we observe that standard cell device scaling...
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9798831/ |
| _version_ | 1818217525692858368 |
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| author | Chung-Kuan Cheng Chia-Tung Ho Daeyeal Lee Bill Lin |
| author_facet | Chung-Kuan Cheng Chia-Tung Ho Daeyeal Lee Bill Lin |
| author_sort | Chung-Kuan Cheng |
| collection | DOAJ |
| description | Continued scaling in accordance with Moore’s law is becoming increasingly difficult. Pitch shrinkage and standard cell height reduction via design technology co-optimization with design rules have sustained this scaling until recently. However, we observe that standard cell device scaling is becoming saturated due to yield and cost. One way to continue device footprint reduction is by expanding in the third dimension via monolithic 3D integration, using for example stacked gate-all-around (GAA) devices, complementary FETs, vertical FETs, and 3D logic. However, using these footprint scaling approaches to increase device density creates new problems. Using vertical gate-all-around FET (VFET) technologies as a specific instance of 3D device scaling, we demonstrate that the key bottleneck to footprint scaling is the <italic>pin density wall</italic>. The footprint of a block is predominantly limited by the pin density as we increase the number of active device layers. While a full-blown paradigm shift on layout methodology, design flow, and electronic design automation (EDA) platform is not available now, we describe in this article three specific baby steps that can alleviate the pin density problem and demonstrate their potential benefits for footprint scaling: (1) allocating standard cell pin sideways and using block-level routing with the local interconnect layers; (2) using the backside of the substrate for the power distribution network; and (3) using the generation of more complex standard cells. We show via several core designs that a 42.6% reduction in the core area is achievable when a combination of these operations is employed. |
| first_indexed | 2024-12-12T07:09:15Z |
| format | Article |
| id | doaj.art-bdca7c1885e04fe0b1c71b223a500dd4 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-12T07:09:15Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-bdca7c1885e04fe0b1c71b223a500dd42022-12-22T00:33:40ZengIEEEIEEE Access2169-35362022-01-0110659716598110.1109/ACCESS.2022.31840089798831Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA PlatformChung-Kuan Cheng0https://orcid.org/0000-0002-9865-8390Chia-Tung Ho1https://orcid.org/0000-0002-6479-7552Daeyeal Lee2https://orcid.org/0000-0003-0778-0110Bill Lin3Department of Computer Science and Engineering, University of California at San Diego, La Jolla, CA, USADepartment of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USADepartment of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USADepartment of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USAContinued scaling in accordance with Moore’s law is becoming increasingly difficult. Pitch shrinkage and standard cell height reduction via design technology co-optimization with design rules have sustained this scaling until recently. However, we observe that standard cell device scaling is becoming saturated due to yield and cost. One way to continue device footprint reduction is by expanding in the third dimension via monolithic 3D integration, using for example stacked gate-all-around (GAA) devices, complementary FETs, vertical FETs, and 3D logic. However, using these footprint scaling approaches to increase device density creates new problems. Using vertical gate-all-around FET (VFET) technologies as a specific instance of 3D device scaling, we demonstrate that the key bottleneck to footprint scaling is the <italic>pin density wall</italic>. The footprint of a block is predominantly limited by the pin density as we increase the number of active device layers. While a full-blown paradigm shift on layout methodology, design flow, and electronic design automation (EDA) platform is not available now, we describe in this article three specific baby steps that can alleviate the pin density problem and demonstrate their potential benefits for footprint scaling: (1) allocating standard cell pin sideways and using block-level routing with the local interconnect layers; (2) using the backside of the substrate for the power distribution network; and (3) using the generation of more complex standard cells. We show via several core designs that a 42.6% reduction in the core area is achievable when a combination of these operations is employed.https://ieeexplore.ieee.org/document/9798831/3D integrationDTCOpin-density wallrouting congestionSTCOVFET |
| spellingShingle | Chung-Kuan Cheng Chia-Tung Ho Daeyeal Lee Bill Lin Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform IEEE Access 3D integration DTCO pin-density wall routing congestion STCO VFET |
| title | Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform |
| title_full | Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform |
| title_fullStr | Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform |
| title_full_unstemmed | Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform |
| title_short | Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform |
| title_sort | monolithic 3d semiconductor footprint scaling exploration based on vfet standard cell layout methodology design flow and eda platform |
| topic | 3D integration DTCO pin-density wall routing congestion STCO VFET |
| url | https://ieeexplore.ieee.org/document/9798831/ |
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