A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications

In this paper, a high performance adaptive digital low-dropout voltage regulator (ADLDO) is proposed for Internet-of-Things (IoT) applications. In the proposed ADLDO, a fully synthesizable adaptive digital controller is designed. It automatically senses load variations and adaptively controls multi-...

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Main Authors: Muhammad Asif, Imran Ali, Danial Khan, Muhammad Riaz Ur Rehman, Qurat- Ul-Ain, Muhammad Basim, Young Gun Pu, Minjae Lee, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/9141235/
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author Muhammad Asif
Imran Ali
Danial Khan
Muhammad Riaz Ur Rehman
Qurat- Ul-Ain
Muhammad Basim
Young Gun Pu
Minjae Lee
Keum Cheol Hwang
Youngoo Yang
Kang-Yoon Lee
author_facet Muhammad Asif
Imran Ali
Danial Khan
Muhammad Riaz Ur Rehman
Qurat- Ul-Ain
Muhammad Basim
Young Gun Pu
Minjae Lee
Keum Cheol Hwang
Youngoo Yang
Kang-Yoon Lee
author_sort Muhammad Asif
collection DOAJ
description In this paper, a high performance adaptive digital low-dropout voltage regulator (ADLDO) is proposed for Internet-of-Things (IoT) applications. In the proposed ADLDO, a fully synthesizable adaptive digital controller is designed. It automatically senses load variations and adaptively controls multi-loop architecture to reduce quiescent current, minimize output voltage ripples and achieve fast transient response. The multi-loop architecture with hill climbing reduces the total bi-directional shift registers length which results in the reduced leakage current in the transistor-switch-array (TSA), and improves the recovery time and output DC voltage accuracy. A dithering technique is introduced to eliminate the limit cycle oscillation (LCO) and improve the performance of the regulator. The dynamic frequency scaling (DFS) mechanism is proposed for reducing controller power consumption in steady state. In order to reduce the offset and output voltage error, a dynamic latch comparator is utilized. When the input supply voltage is varied from 0.5 V to 1 V, the measured output voltage ranges from 0.45 V to 0.95 V with 50 mV dropout voltage. The operating frequency is 10 MHz with fast transient response and quiescent current of 350 ns and 3.7&#x03BC;A, respectively. The maximum measured power and current efficiencies are 89.7 % and 99.97 %, respectively, with 1.9 mV output voltage ripples. Measured load and line regulations are 2.2 mV/mA and 9.5 mV/V respectively. The proposed circuit is implemented in 28 nm CMOS process and occupies 0.016 mm<sup>2</sup> chip area.
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spelling doaj.art-bdcad6946b444f73889e489651b4ab292022-12-21T18:20:06ZengIEEEIEEE Access2169-35362020-01-01813220013221110.1109/ACCESS.2020.30096019141235A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT ApplicationsMuhammad Asif0https://orcid.org/0000-0002-4888-9721Imran Ali1https://orcid.org/0000-0002-4705-9988Danial Khan2https://orcid.org/0000-0003-4010-2637Muhammad Riaz Ur Rehman3https://orcid.org/0000-0002-2128-0115Qurat- Ul-Ain4https://orcid.org/0000-0001-6223-6535Muhammad Basim5https://orcid.org/0000-0002-0183-2592Young Gun Pu6https://orcid.org/0000-0001-5190-4462Minjae Lee7https://orcid.org/0000-0003-1500-1404Keum Cheol Hwang8https://orcid.org/0000-0002-8074-1137Youngoo Yang9https://orcid.org/0000-0003-3463-0687Kang-Yoon Lee10https://orcid.org/0000-0001-9777-6953Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaSchool of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Gwangju, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaIn this paper, a high performance adaptive digital low-dropout voltage regulator (ADLDO) is proposed for Internet-of-Things (IoT) applications. In the proposed ADLDO, a fully synthesizable adaptive digital controller is designed. It automatically senses load variations and adaptively controls multi-loop architecture to reduce quiescent current, minimize output voltage ripples and achieve fast transient response. The multi-loop architecture with hill climbing reduces the total bi-directional shift registers length which results in the reduced leakage current in the transistor-switch-array (TSA), and improves the recovery time and output DC voltage accuracy. A dithering technique is introduced to eliminate the limit cycle oscillation (LCO) and improve the performance of the regulator. The dynamic frequency scaling (DFS) mechanism is proposed for reducing controller power consumption in steady state. In order to reduce the offset and output voltage error, a dynamic latch comparator is utilized. When the input supply voltage is varied from 0.5 V to 1 V, the measured output voltage ranges from 0.45 V to 0.95 V with 50 mV dropout voltage. The operating frequency is 10 MHz with fast transient response and quiescent current of 350 ns and 3.7&#x03BC;A, respectively. The maximum measured power and current efficiencies are 89.7 % and 99.97 %, respectively, with 1.9 mV output voltage ripples. Measured load and line regulations are 2.2 mV/mA and 9.5 mV/V respectively. The proposed circuit is implemented in 28 nm CMOS process and occupies 0.016 mm<sup>2</sup> chip area.https://ieeexplore.ieee.org/document/9141235/Adaptiveditheringdigital LDOdynamic frequency scaling (DFS)fully synthesizablefast transient
spellingShingle Muhammad Asif
Imran Ali
Danial Khan
Muhammad Riaz Ur Rehman
Qurat- Ul-Ain
Muhammad Basim
Young Gun Pu
Minjae Lee
Keum Cheol Hwang
Youngoo Yang
Kang-Yoon Lee
A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications
IEEE Access
Adaptive
dithering
digital LDO
dynamic frequency scaling (DFS)
fully synthesizable
fast transient
title A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications
title_full A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications
title_fullStr A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications
title_full_unstemmed A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications
title_short A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications
title_sort high performance adaptive digital ldo regulator with dithering and dynamic frequency scaling for iot applications
topic Adaptive
dithering
digital LDO
dynamic frequency scaling (DFS)
fully synthesizable
fast transient
url https://ieeexplore.ieee.org/document/9141235/
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