Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing
In recent years, there has been extensive research on the routing problem of printed circuit boards (PCBs). Due to the increasing number of pins, high pin density, and unique physical constraints, manual PCB routing has become a time-consuming task to achieve design convergence. Previous work decomp...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10274949/ |
| _version_ | 1797655666336202752 |
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| author | Shiyuan Yin Min Jin Gang Chen Guoliang Gong Wenyu Mao Huaxiang Lu |
| author_facet | Shiyuan Yin Min Jin Gang Chen Guoliang Gong Wenyu Mao Huaxiang Lu |
| author_sort | Shiyuan Yin |
| collection | DOAJ |
| description | In recent years, there has been extensive research on the routing problem of printed circuit boards (PCBs). Due to the increasing number of pins, high pin density, and unique physical constraints, manual PCB routing has become a time-consuming task to achieve design convergence. Previous work decomposed the problem into escape routing and area routing, focusing on these problems separately. However, there was always a gap between these two problems, requiring significant human effort for iterative algorithm adjustments. Furthermore, previous area routing work mainly focused on routing between ball grid array (BGA) packages in escape routing. However, in practice, many components are not in the form of BGA packages, such as passive devices, decoupling capacitors, and through-hole pin arrays. Therefore, it is necessary to study a unified routing approach. The current unified routing approach adopts the A* algorithm, but there is still room for improvement in routing speed. This paper proposes a new algorithm called Unet-Astar, which accelerates the routing efficiency by employing deep learning algorithms in a simulated environment. Additionally, a Deeper Unet is proposed for generating recommended regions for the routing algorithm. The new network structure can provide more contextual information, thereby improving routing efficiency. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm. Specifically, for all given test cases, our router achieves approximately a 70% improvement in runtime speed compared to the old router. Another major contribution of this work is the development of a routing problem set generator, which can generate parameterized routing problem sets with different sizes and constraints. This enables the evaluation of different routing algorithms and the generation of training datasets for future data-driven routing methods. All the code has been open-sourced and can be found at <uri>https://github.com/Firesuiry/Unet-Astar-For-PCB-Routing</uri>. |
| first_indexed | 2024-03-11T17:17:50Z |
| format | Article |
| id | doaj.art-be16200414264fe48da8f179bd034013 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-11T17:17:50Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-be16200414264fe48da8f179bd0340132023-10-19T23:01:39ZengIEEEIEEE Access2169-35362023-01-011111371211372510.1109/ACCESS.2023.332358910274949Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB RoutingShiyuan Yin0https://orcid.org/0000-0002-9437-7807Min Jin1Gang Chen2https://orcid.org/0000-0003-3157-0172Guoliang Gong3Wenyu Mao4Huaxiang Lu5High-Speed Circuit and Neural Network Laboratory, Institute of Semiconductors, Chinese Academy of Sciences (CAS), Beijing, ChinaHigh-Speed Circuit and Neural Network Laboratory, Institute of Semiconductors, Chinese Academy of Sciences (CAS), Beijing, ChinaHigh-Speed Circuit and Neural Network Laboratory, Institute of Semiconductors, Chinese Academy of Sciences (CAS), Beijing, ChinaHigh-Speed Circuit and Neural Network Laboratory, Institute of Semiconductors, Chinese Academy of Sciences (CAS), Beijing, ChinaHigh-Speed Circuit and Neural Network Laboratory, Institute of Semiconductors, Chinese Academy of Sciences (CAS), Beijing, ChinaHigh-Speed Circuit and Neural Network Laboratory, Institute of Semiconductors, Chinese Academy of Sciences (CAS), Beijing, ChinaIn recent years, there has been extensive research on the routing problem of printed circuit boards (PCBs). Due to the increasing number of pins, high pin density, and unique physical constraints, manual PCB routing has become a time-consuming task to achieve design convergence. Previous work decomposed the problem into escape routing and area routing, focusing on these problems separately. However, there was always a gap between these two problems, requiring significant human effort for iterative algorithm adjustments. Furthermore, previous area routing work mainly focused on routing between ball grid array (BGA) packages in escape routing. However, in practice, many components are not in the form of BGA packages, such as passive devices, decoupling capacitors, and through-hole pin arrays. Therefore, it is necessary to study a unified routing approach. The current unified routing approach adopts the A* algorithm, but there is still room for improvement in routing speed. This paper proposes a new algorithm called Unet-Astar, which accelerates the routing efficiency by employing deep learning algorithms in a simulated environment. Additionally, a Deeper Unet is proposed for generating recommended regions for the routing algorithm. The new network structure can provide more contextual information, thereby improving routing efficiency. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm. Specifically, for all given test cases, our router achieves approximately a 70% improvement in runtime speed compared to the old router. Another major contribution of this work is the development of a routing problem set generator, which can generate parameterized routing problem sets with different sizes and constraints. This enables the evaluation of different routing algorithms and the generation of training datasets for future data-driven routing methods. All the code has been open-sourced and can be found at <uri>https://github.com/Firesuiry/Unet-Astar-For-PCB-Routing</uri>.https://ieeexplore.ieee.org/document/10274949/Physical designprinted circuit boardroutingmachine learning |
| spellingShingle | Shiyuan Yin Min Jin Gang Chen Guoliang Gong Wenyu Mao Huaxiang Lu Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing IEEE Access Physical design printed circuit board routing machine learning |
| title | Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing |
| title_full | Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing |
| title_fullStr | Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing |
| title_full_unstemmed | Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing |
| title_short | Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing |
| title_sort | unet astar a deep learning based fast routing algorithm for unified pcb routing |
| topic | Physical design printed circuit board routing machine learning |
| url | https://ieeexplore.ieee.org/document/10274949/ |
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