The HERA Methodology: Reconfigurable Logic in General-Purpose Computing
Due to the ongoing slowdown of Dennard scaling, heterogeneous hardware architectures are inevitable to meet the increasing demand for energy efficient systems. However, one of the most important aspects that shape today’s computing landscape is the wide availability of software that can r...
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9591561/ |
| _version_ | 1818424559633694720 |
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| author | Philipp Holzinger Marc Reichenbach |
| author_facet | Philipp Holzinger Marc Reichenbach |
| author_sort | Philipp Holzinger |
| collection | DOAJ |
| description | Due to the ongoing slowdown of Dennard scaling, heterogeneous hardware architectures are inevitable to meet the increasing demand for energy efficient systems. However, one of the most important aspects that shape today’s computing landscape is the wide availability of software that can run on any system. Current applications that use accelerators, in contrast, are often especially tailored to a specific hardware setup and therefore not universally deployable. This is particularly true for reconfigurable logic as their internal structure requires the circuits and their integration to be designed as well. This makes them inherently difficult to use and therefore less accessible for a general audience. Nevertheless, their balance of flexibility and efficiency puts reconfigurable accelerators in a unique position between CPUs, GPUs, and ASICs. Therefore, one of the main challenges of future heterogeneous systems is to foster collaborative computing between these vastly different components while still being simple to use. Previous approaches mostly focused on subproblems instead of a holistic view of hardware and software in the context of commonplace usability. This paper analyzes the general demands on a reconfigurable platform and derives their requirements regarding accessibility and security. Hereby, we investigate several key features like hardware virtualization, system shared virtual memory, and the use of wide-spread programming paradigms. Then, we systematically build up such a platform based on the established ROCm GPU framework and its internal HSA standard. This new common HERA methodology is finally also demonstrated as a prototype. |
| first_indexed | 2024-12-14T13:59:58Z |
| format | Article |
| id | doaj.art-bed5cbdc5b1e4c568f9d2583a4c47cb7 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-14T13:59:58Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-bed5cbdc5b1e4c568f9d2583a4c47cb72022-12-21T22:58:44ZengIEEEIEEE Access2169-35362021-01-01914721214723610.1109/ACCESS.2021.31238749591561The HERA Methodology: Reconfigurable Logic in General-Purpose ComputingPhilipp Holzinger0https://orcid.org/0000-0002-2912-0650Marc Reichenbach1https://orcid.org/0000-0002-9687-6247Chair of Computer Architecture, Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, GermanyChair of Computer Engineering, Brandenburg University of Technology Cottbus-Senftenberg, Cottbus, GermanyDue to the ongoing slowdown of Dennard scaling, heterogeneous hardware architectures are inevitable to meet the increasing demand for energy efficient systems. However, one of the most important aspects that shape today’s computing landscape is the wide availability of software that can run on any system. Current applications that use accelerators, in contrast, are often especially tailored to a specific hardware setup and therefore not universally deployable. This is particularly true for reconfigurable logic as their internal structure requires the circuits and their integration to be designed as well. This makes them inherently difficult to use and therefore less accessible for a general audience. Nevertheless, their balance of flexibility and efficiency puts reconfigurable accelerators in a unique position between CPUs, GPUs, and ASICs. Therefore, one of the main challenges of future heterogeneous systems is to foster collaborative computing between these vastly different components while still being simple to use. Previous approaches mostly focused on subproblems instead of a holistic view of hardware and software in the context of commonplace usability. This paper analyzes the general demands on a reconfigurable platform and derives their requirements regarding accessibility and security. Hereby, we investigate several key features like hardware virtualization, system shared virtual memory, and the use of wide-spread programming paradigms. Then, we systematically build up such a platform based on the established ROCm GPU framework and its internal HSA standard. This new common HERA methodology is finally also demonstrated as a prototype.https://ieeexplore.ieee.org/document/9591561/Automatic synthesishardware/software interfacesheterogeneous systemsreconfigurable hardwarevirtual memory |
| spellingShingle | Philipp Holzinger Marc Reichenbach The HERA Methodology: Reconfigurable Logic in General-Purpose Computing IEEE Access Automatic synthesis hardware/software interfaces heterogeneous systems reconfigurable hardware virtual memory |
| title | The HERA Methodology: Reconfigurable Logic in General-Purpose Computing |
| title_full | The HERA Methodology: Reconfigurable Logic in General-Purpose Computing |
| title_fullStr | The HERA Methodology: Reconfigurable Logic in General-Purpose Computing |
| title_full_unstemmed | The HERA Methodology: Reconfigurable Logic in General-Purpose Computing |
| title_short | The HERA Methodology: Reconfigurable Logic in General-Purpose Computing |
| title_sort | hera methodology reconfigurable logic in general purpose computing |
| topic | Automatic synthesis hardware/software interfaces heterogeneous systems reconfigurable hardware virtual memory |
| url | https://ieeexplore.ieee.org/document/9591561/ |
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