Implementation of NoC on FPGA with Area and Power Optimization
On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size, speed, power and area. The goal of working wa...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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European Alliance for Innovation (EAI)
2019-03-01
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| Series: | EAI Endorsed Transactions on Context-aware Systems and Applications |
| Subjects: | |
| Online Access: | https://eudl.eu/pdf/10.4108/eai.23-5-2019.158953 |
| _version_ | 1818064596213170176 |
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| author | Momil Ijaz Huma Urooj Muhammad Sethi |
| author_facet | Momil Ijaz Huma Urooj Muhammad Sethi |
| author_sort | Momil Ijaz |
| collection | DOAJ |
| description | On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size, speed, power and area. The goal of working was to design a usable and researchable general-purpose 2x2 mesh NoC architecture, which is not application specific, and have optimized area and power. Desired NoC was coded and deployed on FPGA Spartan-3 kit in a generic mode, with the efficient area and power utilization than traditional deployments. |
| first_indexed | 2024-12-10T14:38:30Z |
| format | Article |
| id | doaj.art-bf41b69bec5041e69bb9ba264b71cfdb |
| institution | Directory Open Access Journal |
| issn | 2409-0026 |
| language | English |
| last_indexed | 2024-12-10T14:38:30Z |
| publishDate | 2019-03-01 |
| publisher | European Alliance for Innovation (EAI) |
| record_format | Article |
| series | EAI Endorsed Transactions on Context-aware Systems and Applications |
| spelling | doaj.art-bf41b69bec5041e69bb9ba264b71cfdb2022-12-22T01:44:46ZengEuropean Alliance for Innovation (EAI)EAI Endorsed Transactions on Context-aware Systems and Applications2409-00262019-03-0161610.4108/eai.23-5-2019.158953Implementation of NoC on FPGA with Area and Power OptimizationMomil Ijaz0Huma Urooj1Muhammad Sethi2Department of Computer Systems Engineering, University of Engineering and Technology, Peshawar, PakistanDepartment of Computer Systems Engineering, University of Engineering and Technology, Peshawar, PakistanDepartment of Computer Systems Engineering, University of Engineering and Technology, Peshawar, PakistanOn-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size, speed, power and area. The goal of working was to design a usable and researchable general-purpose 2x2 mesh NoC architecture, which is not application specific, and have optimized area and power. Desired NoC was coded and deployed on FPGA Spartan-3 kit in a generic mode, with the efficient area and power utilization than traditional deployments.https://eudl.eu/pdf/10.4108/eai.23-5-2019.158953Network on chipnodeswitchingpacketcrossbar |
| spellingShingle | Momil Ijaz Huma Urooj Muhammad Sethi Implementation of NoC on FPGA with Area and Power Optimization EAI Endorsed Transactions on Context-aware Systems and Applications Network on chip node switching packet crossbar |
| title | Implementation of NoC on FPGA with Area and Power Optimization |
| title_full | Implementation of NoC on FPGA with Area and Power Optimization |
| title_fullStr | Implementation of NoC on FPGA with Area and Power Optimization |
| title_full_unstemmed | Implementation of NoC on FPGA with Area and Power Optimization |
| title_short | Implementation of NoC on FPGA with Area and Power Optimization |
| title_sort | implementation of noc on fpga with area and power optimization |
| topic | Network on chip node switching packet crossbar |
| url | https://eudl.eu/pdf/10.4108/eai.23-5-2019.158953 |
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